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phy: phy-mt65xx-usb3: add PCIe PHY support
This patch adds PCIe PHY setting part. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Ryder Lee
Kishon Vijay Abraham I
parent
325ce0fe58
commit
44a6d6ce64
@ -29,7 +29,7 @@
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#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
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/* u2 phy bank */
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#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
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/* u3 phy banks */
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/* u3/pcie phy banks */
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#define SSUSB_SIFSLV_V1_U3PHYD 0x000
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#define SSUSB_SIFSLV_V1_U3PHYA 0x200
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@ -99,6 +99,23 @@
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#define P2C_RG_SESSEND BIT(4)
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#define P2C_RG_AVALID BIT(2)
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#define U3P_U3_CHIP_GPIO_CTLD 0x0c
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#define P3C_REG_IP_SW_RST BIT(31)
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#define P3C_MCU_BUS_CK_GATE_EN BIT(30)
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#define P3C_FORCE_IP_SW_RST BIT(29)
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#define U3P_U3_CHIP_GPIO_CTLE 0x10
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#define P3C_RG_SWRST_U3_PHYD BIT(25)
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#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
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#define U3P_U3_PHYA_REG0 0x000
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#define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
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#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
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#define U3P_U3_PHYA_REG1 0x004
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#define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
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#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
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#define U3P_U3_PHYA_REG6 0x018
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#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
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#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
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@ -108,9 +125,40 @@
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#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
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#define U3P_U3_PHYA_DA_REG0 0x100
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#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
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#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
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#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
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#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
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#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
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#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
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#define U3P_U3_PHYA_DA_REG4 0x108
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#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
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#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
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#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
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#define U3P_U3_PHYA_DA_REG5 0x10c
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#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
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#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
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#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
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#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
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#define U3P_U3_PHYA_DA_REG6 0x110
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#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
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#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
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#define U3P_U3_PHYA_DA_REG7 0x114
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#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
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#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
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#define U3P_U3_PHYA_DA_REG20 0x13c
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#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
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#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
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#define U3P_U3_PHYA_DA_REG25 0x148
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#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
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#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
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#define U3P_U3_PHYD_LFPS1 0x00c
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#define P3D_RG_FWAKE_TH GENMASK(21, 16)
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#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
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@ -322,7 +370,7 @@ static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy,
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dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index);
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}
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static void phy_instance_init(struct mt65xx_u3phy *u3phy,
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static void u2_phy_instance_init(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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@ -384,7 +432,7 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
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dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
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}
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static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
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static void u2_phy_instance_power_on(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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@ -420,7 +468,7 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
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dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
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}
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static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
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static void u2_phy_instance_power_off(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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@ -458,7 +506,7 @@ static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
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dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
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}
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static void phy_instance_exit(struct mt65xx_u3phy *u3phy,
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static void u2_phy_instance_exit(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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@ -477,21 +525,133 @@ static void phy_instance_exit(struct mt65xx_u3phy *u3phy,
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}
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}
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static void pcie_phy_instance_init(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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struct u3phy_banks *u3_banks = &instance->u3_banks;
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u32 tmp;
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if (u3phy->pdata->version != MT_PHY_V1)
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return;
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
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tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
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tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
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/* ref clk drive */
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);
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tmp &= ~P3A_RG_CLKDRV_AMP;
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tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
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tmp &= ~P3A_RG_CLKDRV_OFF;
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tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
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/* SSC delta -5000ppm */
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);
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tmp &= ~P3A_RG_PLL_DELTA1_PE2H;
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tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);
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tmp &= ~P3A_RG_PLL_DELTA_PE2H;
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tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);
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/* change pll BW 0.6M */
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);
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tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H);
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tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);
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tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H);
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tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);
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tmp &= ~P3A_RG_PLL_IR_PE2H;
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tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);
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tmp &= ~P3A_RG_PLL_BP_PE2H;
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tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);
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/* Tx Detect Rx Timing: 10us -> 5us */
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
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tmp &= ~P3D_RG_RXDET_STB2_SET;
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tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
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tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
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tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
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/* wait for PCIe subsys register to active */
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usleep_range(2500, 3000);
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dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index);
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}
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static void pcie_phy_instance_power_on(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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struct u3phy_banks *bank = &instance->u3_banks;
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u32 tmp;
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tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
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tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN |
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P3C_REG_IP_SW_RST);
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writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
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tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
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tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
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writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
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}
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static void pcie_phy_instance_power_off(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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struct u3phy_banks *bank = &instance->u3_banks;
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u32 tmp;
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tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
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tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST;
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writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
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tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
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tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD;
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writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
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}
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static void phy_v1_banks_init(struct mt65xx_u3phy *u3phy,
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struct mt65xx_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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struct u3phy_banks *u3_banks = &instance->u3_banks;
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if (instance->type == PHY_TYPE_USB2) {
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switch (instance->type) {
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case PHY_TYPE_USB2:
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u2_banks->misc = NULL;
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u2_banks->fmreg = u3phy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
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u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
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} else if (instance->type == PHY_TYPE_USB3) {
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break;
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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u3_banks->spllc = u3phy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
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u3_banks->chip = NULL;
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u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
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u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
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break;
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default:
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dev_err(u3phy->dev, "incompatible PHY type\n");
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return;
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}
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}
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@ -501,15 +661,22 @@ static void phy_v2_banks_init(struct mt65xx_u3phy *u3phy,
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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struct u3phy_banks *u3_banks = &instance->u3_banks;
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if (instance->type == PHY_TYPE_USB2) {
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switch (instance->type) {
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case PHY_TYPE_USB2:
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u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
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u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
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u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
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} else if (instance->type == PHY_TYPE_USB3) {
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break;
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
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u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
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u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
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u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
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break;
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default:
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dev_err(u3phy->dev, "incompatible PHY type\n");
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return;
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}
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}
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@ -531,10 +698,20 @@ static int mt65xx_phy_init(struct phy *phy)
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return ret;
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}
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if (instance->type == PHY_TYPE_USB2)
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phy_instance_init(u3phy, instance);
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else
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switch (instance->type) {
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case PHY_TYPE_USB2:
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u2_phy_instance_init(u3phy, instance);
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break;
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case PHY_TYPE_USB3:
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u3_phy_instance_init(u3phy, instance);
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break;
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case PHY_TYPE_PCIE:
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pcie_phy_instance_init(u3phy, instance);
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break;
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default:
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dev_err(u3phy->dev, "incompatible PHY type\n");
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return -EINVAL;
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}
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return 0;
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}
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@ -545,9 +722,12 @@ static int mt65xx_phy_power_on(struct phy *phy)
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struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
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if (instance->type == PHY_TYPE_USB2) {
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phy_instance_power_on(u3phy, instance);
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u2_phy_instance_power_on(u3phy, instance);
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hs_slew_rate_calibrate(u3phy, instance);
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} else if (instance->type == PHY_TYPE_PCIE) {
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pcie_phy_instance_power_on(u3phy, instance);
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}
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return 0;
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}
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@ -557,7 +737,9 @@ static int mt65xx_phy_power_off(struct phy *phy)
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struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
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if (instance->type == PHY_TYPE_USB2)
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phy_instance_power_off(u3phy, instance);
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u2_phy_instance_power_off(u3phy, instance);
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else if (instance->type == PHY_TYPE_PCIE)
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pcie_phy_instance_power_off(u3phy, instance);
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return 0;
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}
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@ -568,7 +750,7 @@ static int mt65xx_phy_exit(struct phy *phy)
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struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
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if (instance->type == PHY_TYPE_USB2)
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phy_instance_exit(u3phy, instance);
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u2_phy_instance_exit(u3phy, instance);
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clk_disable_unprepare(instance->ref_clk);
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clk_disable_unprepare(u3phy->u3phya_ref);
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@ -601,7 +783,8 @@ static struct phy *mt65xx_phy_xlate(struct device *dev,
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instance->type = args->args[0];
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if (!(instance->type == PHY_TYPE_USB2 ||
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instance->type == PHY_TYPE_USB3)) {
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instance->type == PHY_TYPE_USB3 ||
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instance->type == PHY_TYPE_PCIE)) {
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dev_err(dev, "unsupported device type: %d\n", instance->type);
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return ERR_PTR(-EINVAL);
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}
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||||
@ -626,7 +809,7 @@ static const struct phy_ops mt65xx_u3phy_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct mt65xx_phy_pdata mt2701_pdata = {
|
||||
static const struct mt65xx_phy_pdata tphy_v1_pdata = {
|
||||
.avoid_rx_sen_degradation = false,
|
||||
.version = MT_PHY_V1,
|
||||
};
|
||||
@ -642,9 +825,10 @@ static const struct mt65xx_phy_pdata mt8173_pdata = {
|
||||
};
|
||||
|
||||
static const struct of_device_id mt65xx_u3phy_id_table[] = {
|
||||
{ .compatible = "mediatek,mt2701-u3phy", .data = &mt2701_pdata },
|
||||
{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
|
||||
{ .compatible = "mediatek,mt2712-u3phy", .data = &mt2712_pdata },
|
||||
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
|
||||
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user