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drm/radeon/dpm: properly enable/disable vce when vce pg is enabled
The adds the appropriate function calls to properly re-init vce before it's used after it has been power gated. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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03afe6f648
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@ -1412,7 +1412,6 @@ static int kv_update_vce_dpm(struct radeon_device *rdev,
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if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) {
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kv_dpm_powergate_vce(rdev, false);
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/* XXX cik_vce_resume(); */
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if (pi->caps_stable_p_state)
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pi->vce_boot_level = table->count - 1;
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else
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@ -1435,7 +1434,6 @@ static int kv_update_vce_dpm(struct radeon_device *rdev,
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kv_enable_vce_dpm(rdev, true);
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} else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) {
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kv_enable_vce_dpm(rdev, false);
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/* XXX cik_vce_suspend(); */
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kv_dpm_powergate_vce(rdev, true);
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}
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@ -1575,11 +1573,16 @@ static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
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pi->vce_power_gated = gate;
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if (gate) {
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if (pi->caps_vce_pg)
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if (pi->caps_vce_pg) {
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/* XXX do we need a vce_v1_0_stop() ? */
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kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
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}
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} else {
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if (pi->caps_vce_pg)
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if (pi->caps_vce_pg) {
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kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
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vce_v2_0_resume(rdev);
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vce_v1_0_start(rdev);
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}
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}
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}
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