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Merge branch 'x86/grand-schemozzle' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull pti updates from Thomas Gleixner: "The performance deterioration departement is not proud at all to present yet another set of speculation fences to mitigate the next chapter in the 'what could possibly go wrong' story. The new vulnerability belongs to the Spectre class and affects GS based data accesses and has therefore been dubbed 'Grand Schemozzle' for secret communication purposes. It's officially listed as CVE-2019-1125. Conditional branches in the entry paths which contain a SWAPGS instruction (interrupts and exceptions) can be mis-speculated which results in speculative accesses with a wrong GS base. This can happen on entry from user mode through a mis-speculated branch which takes the entry from kernel mode path and therefore does not execute the SWAPGS instruction. The following speculative accesses are done with user GS base. On entry from kernel mode the mis-speculated branch executes the SWAPGS instruction in the entry from user mode path which has the same effect that the following GS based accesses are done with user GS base. If there is a disclosure gadget available in these code paths the mis-speculated data access can be leaked through the usual side channels. The entry from user mode issue affects all CPUs which have speculative execution. The entry from kernel mode issue affects only Intel CPUs which can speculate through SWAPGS. On CPUs from other vendors SWAPGS has semantics which prevent that. SMAP migitates both problems but only when the CPU is not affected by the Meltdown vulnerability. The mitigation is to issue LFENCE instructions in the entry from kernel mode path for all affected CPUs and on the affected Intel CPUs also in the entry from user mode path unless PTI is enabled because the CR3 write is serializing. The fences are as usual enabled conditionally and can be completely disabled on the kernel command line. The Spectre V1 documentation is updated accordingly. A big "Thank You!" goes to Josh for doing the heavy lifting for this round of hardware misfeature 'repair'. Of course also "Thank You!" to everybody else who contributed in one way or the other" * 'x86/grand-schemozzle' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Documentation: Add swapgs description to the Spectre v1 documentation x86/speculation/swapgs: Exclude ATOMs from speculation through SWAPGS x86/entry/64: Use JMP instead of JMPQ x86/speculation: Enable Spectre v1 swapgs mitigations x86/speculation: Prepare entry code for Spectre v1 swapgs mitigations
This commit is contained in:
Linus Torvalds
commit
4368c4bc9d
@ -41,10 +41,11 @@ Related CVEs
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The following CVE entries describe Spectre variants:
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============= ======================= =================
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============= ======================= ==========================
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CVE-2017-5753 Bounds check bypass Spectre variant 1
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CVE-2017-5715 Branch target injection Spectre variant 2
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============= ======================= =================
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CVE-2019-1125 Spectre v1 swapgs Spectre variant 1 (swapgs)
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============= ======================= ==========================
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Problem
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-------
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@ -78,6 +79,13 @@ There are some extensions of Spectre variant 1 attacks for reading data
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over the network, see :ref:`[12] <spec_ref12>`. However such attacks
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are difficult, low bandwidth, fragile, and are considered low risk.
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Note that, despite "Bounds Check Bypass" name, Spectre variant 1 is not
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only about user-controlled array bounds checks. It can affect any
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conditional checks. The kernel entry code interrupt, exception, and NMI
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handlers all have conditional swapgs checks. Those may be problematic
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in the context of Spectre v1, as kernel code can speculatively run with
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a user GS.
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Spectre variant 2 (Branch Target Injection)
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-------------------------------------------
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@ -132,6 +140,9 @@ not cover all possible attack vectors.
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1. A user process attacking the kernel
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Spectre variant 1
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~~~~~~~~~~~~~~~~~
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The attacker passes a parameter to the kernel via a register or
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via a known address in memory during a syscall. Such parameter may
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be used later by the kernel as an index to an array or to derive
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@ -144,7 +155,40 @@ not cover all possible attack vectors.
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potentially be influenced for Spectre attacks, new "nospec" accessor
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macros are used to prevent speculative loading of data.
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Spectre variant 2 attacker can :ref:`poison <poison_btb>` the branch
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Spectre variant 1 (swapgs)
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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An attacker can train the branch predictor to speculatively skip the
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swapgs path for an interrupt or exception. If they initialize
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the GS register to a user-space value, if the swapgs is speculatively
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skipped, subsequent GS-related percpu accesses in the speculation
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window will be done with the attacker-controlled GS value. This
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could cause privileged memory to be accessed and leaked.
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For example:
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::
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if (coming from user space)
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swapgs
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mov %gs:<percpu_offset>, %reg
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mov (%reg), %reg1
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When coming from user space, the CPU can speculatively skip the
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swapgs, and then do a speculative percpu load using the user GS
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value. So the user can speculatively force a read of any kernel
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value. If a gadget exists which uses the percpu value as an address
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in another load/store, then the contents of the kernel value may
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become visible via an L1 side channel attack.
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A similar attack exists when coming from kernel space. The CPU can
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speculatively do the swapgs, causing the user GS to get used for the
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rest of the speculative window.
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Spectre variant 2
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~~~~~~~~~~~~~~~~~
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A spectre variant 2 attacker can :ref:`poison <poison_btb>` the branch
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target buffer (BTB) before issuing syscall to launch an attack.
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After entering the kernel, the kernel could use the poisoned branch
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target buffer on indirect jump and jump to gadget code in speculative
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@ -280,11 +324,18 @@ The sysfs file showing Spectre variant 1 mitigation status is:
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The possible values in this file are:
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======================================= =================================
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'Mitigation: __user pointer sanitation' Protection in kernel on a case by
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case base with explicit pointer
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sanitation.
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======================================= =================================
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.. list-table::
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* - 'Not affected'
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- The processor is not vulnerable.
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* - 'Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers'
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- The swapgs protections are disabled; otherwise it has
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protection in the kernel on a case by case base with explicit
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pointer sanitation and usercopy LFENCE barriers.
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* - 'Mitigation: usercopy/swapgs barriers and __user pointer sanitization'
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- Protection in the kernel on a case by case base with explicit
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pointer sanitation, usercopy LFENCE barriers, and swapgs LFENCE
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barriers.
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However, the protections are put in place on a case by case basis,
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and there is no guarantee that all possible attack vectors for Spectre
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@ -366,12 +417,27 @@ Turning on mitigation for Spectre variant 1 and Spectre variant 2
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1. Kernel mitigation
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^^^^^^^^^^^^^^^^^^^^
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Spectre variant 1
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~~~~~~~~~~~~~~~~~
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For the Spectre variant 1, vulnerable kernel code (as determined
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by code audit or scanning tools) is annotated on a case by case
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basis to use nospec accessor macros for bounds clipping :ref:`[2]
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<spec_ref2>` to avoid any usable disclosure gadgets. However, it may
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not cover all attack vectors for Spectre variant 1.
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Copy-from-user code has an LFENCE barrier to prevent the access_ok()
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check from being mis-speculated. The barrier is done by the
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barrier_nospec() macro.
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For the swapgs variant of Spectre variant 1, LFENCE barriers are
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added to interrupt, exception and NMI entry where needed. These
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barriers are done by the FENCE_SWAPGS_KERNEL_ENTRY and
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FENCE_SWAPGS_USER_ENTRY macros.
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Spectre variant 2
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~~~~~~~~~~~~~~~~~
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For Spectre variant 2 mitigation, the compiler turns indirect calls or
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jumps in the kernel into equivalent return trampolines (retpolines)
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:ref:`[3] <spec_ref3>` :ref:`[9] <spec_ref9>` to go to the target
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@ -473,6 +539,12 @@ Mitigation control on the kernel command line
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Spectre variant 2 mitigation can be disabled or force enabled at the
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kernel command line.
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nospectre_v1
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[X86,PPC] Disable mitigations for Spectre Variant 1
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(bounds check bypass). With this option data leaks are
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possible in the system.
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nospectre_v2
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[X86] Disable all mitigations for the Spectre variant 2
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@ -2604,7 +2604,7 @@
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expose users to several CPU vulnerabilities.
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Equivalent to: nopti [X86,PPC]
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kpti=0 [ARM64]
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nospectre_v1 [PPC]
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nospectre_v1 [X86,PPC]
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nobp=0 [S390]
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nospectre_v2 [X86,PPC,S390,ARM64]
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spectre_v2_user=off [X86]
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@ -2965,9 +2965,9 @@
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nosmt=force: Force disable SMT, cannot be undone
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via the sysfs control file.
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nospectre_v1 [PPC] Disable mitigations for Spectre Variant 1 (bounds
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check bypass). With this option data leaks are possible
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in the system.
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nospectre_v1 [X86,PPC] Disable mitigations for Spectre Variant 1
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(bounds check bypass). With this option data leaks are
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possible in the system.
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nospectre_v2 [X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for
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the Spectre variant 2 (indirect branch prediction)
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@ -314,6 +314,23 @@ For 32-bit we have the following conventions - kernel is built with
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#endif
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/*
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* Mitigate Spectre v1 for conditional swapgs code paths.
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*
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* FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
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* prevent a speculative swapgs when coming from kernel space.
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*
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* FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
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* to prevent the swapgs from getting speculatively skipped when coming from
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* user space.
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*/
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.macro FENCE_SWAPGS_USER_ENTRY
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ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
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.endm
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.macro FENCE_SWAPGS_KERNEL_ENTRY
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ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
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.endm
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.macro STACKLEAK_ERASE_NOCLOBBER
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#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
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PUSH_AND_CLEAR_REGS
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@ -519,7 +519,7 @@ ENTRY(interrupt_entry)
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testb $3, CS-ORIG_RAX+8(%rsp)
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jz 1f
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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/*
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* Switch to the thread stack. The IRET frame and orig_ax are
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* on the stack, as well as the return address. RDI..R12 are
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@ -549,8 +549,10 @@ ENTRY(interrupt_entry)
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UNWIND_HINT_FUNC
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movq (%rdi), %rdi
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jmp 2f
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1:
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FENCE_SWAPGS_KERNEL_ENTRY
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2:
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PUSH_AND_CLEAR_REGS save_ret=1
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ENCODE_FRAME_POINTER 8
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@ -1238,6 +1240,13 @@ ENTRY(paranoid_entry)
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*/
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SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
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/*
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* The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an
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* unconditional CR3 write, even in the PTI case. So do an lfence
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* to prevent GS speculation, regardless of whether PTI is enabled.
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*/
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FENCE_SWAPGS_KERNEL_ENTRY
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ret
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END(paranoid_entry)
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@ -1288,6 +1297,7 @@ ENTRY(error_entry)
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* from user mode due to an IRET fault.
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*/
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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/* We have user CR3. Change to kernel CR3. */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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@ -1301,6 +1311,8 @@ ENTRY(error_entry)
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pushq %r12
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ret
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.Lerror_entry_done_lfence:
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FENCE_SWAPGS_KERNEL_ENTRY
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.Lerror_entry_done:
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ret
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@ -1318,7 +1330,7 @@ ENTRY(error_entry)
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cmpq %rax, RIP+8(%rsp)
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je .Lbstep_iret
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cmpq $.Lgs_change, RIP+8(%rsp)
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jne .Lerror_entry_done
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jne .Lerror_entry_done_lfence
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/*
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* hack: .Lgs_change can fail with user gsbase. If this happens, fix up
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@ -1326,6 +1338,7 @@ ENTRY(error_entry)
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* .Lgs_change's error handler with kernel gsbase.
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*/
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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jmp .Lerror_entry_done
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@ -1340,6 +1353,7 @@ ENTRY(error_entry)
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* gsbase and CR3. Switch to kernel gsbase and CR3:
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*/
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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/*
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@ -1431,6 +1445,7 @@ ENTRY(nmi)
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swapgs
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cld
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
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movq %rsp, %rdx
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movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
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@ -281,6 +281,8 @@
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#define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
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#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
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#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
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#define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
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#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
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@ -394,5 +396,6 @@
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#define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
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#define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
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#define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */
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#define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
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#endif /* _ASM_X86_CPUFEATURES_H */
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@ -34,6 +34,7 @@
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|
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#include "cpu.h"
|
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|
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static void __init spectre_v1_select_mitigation(void);
|
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static void __init spectre_v2_select_mitigation(void);
|
||||
static void __init ssb_select_mitigation(void);
|
||||
static void __init l1tf_select_mitigation(void);
|
||||
@ -98,17 +99,11 @@ void __init check_bugs(void)
|
||||
if (boot_cpu_has(X86_FEATURE_STIBP))
|
||||
x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
|
||||
|
||||
/* Select the proper spectre mitigation before patching alternatives */
|
||||
/* Select the proper CPU mitigations before patching alternatives: */
|
||||
spectre_v1_select_mitigation();
|
||||
spectre_v2_select_mitigation();
|
||||
|
||||
/*
|
||||
* Select proper mitigation for any exposure to the Speculative Store
|
||||
* Bypass vulnerability.
|
||||
*/
|
||||
ssb_select_mitigation();
|
||||
|
||||
l1tf_select_mitigation();
|
||||
|
||||
mds_select_mitigation();
|
||||
|
||||
arch_smt_update();
|
||||
@ -273,6 +268,98 @@ static int __init mds_cmdline(char *str)
|
||||
}
|
||||
early_param("mds", mds_cmdline);
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "Spectre V1 : " fmt
|
||||
|
||||
enum spectre_v1_mitigation {
|
||||
SPECTRE_V1_MITIGATION_NONE,
|
||||
SPECTRE_V1_MITIGATION_AUTO,
|
||||
};
|
||||
|
||||
static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
|
||||
SPECTRE_V1_MITIGATION_AUTO;
|
||||
|
||||
static const char * const spectre_v1_strings[] = {
|
||||
[SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
|
||||
[SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
|
||||
};
|
||||
|
||||
/*
|
||||
* Does SMAP provide full mitigation against speculative kernel access to
|
||||
* userspace?
|
||||
*/
|
||||
static bool smap_works_speculatively(void)
|
||||
{
|
||||
if (!boot_cpu_has(X86_FEATURE_SMAP))
|
||||
return false;
|
||||
|
||||
/*
|
||||
* On CPUs which are vulnerable to Meltdown, SMAP does not
|
||||
* prevent speculative access to user data in the L1 cache.
|
||||
* Consider SMAP to be non-functional as a mitigation on these
|
||||
* CPUs.
|
||||
*/
|
||||
if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void __init spectre_v1_select_mitigation(void)
|
||||
{
|
||||
if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
|
||||
spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
|
||||
/*
|
||||
* With Spectre v1, a user can speculatively control either
|
||||
* path of a conditional swapgs with a user-controlled GS
|
||||
* value. The mitigation is to add lfences to both code paths.
|
||||
*
|
||||
* If FSGSBASE is enabled, the user can put a kernel address in
|
||||
* GS, in which case SMAP provides no protection.
|
||||
*
|
||||
* [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
|
||||
* FSGSBASE enablement patches have been merged. ]
|
||||
*
|
||||
* If FSGSBASE is disabled, the user can only put a user space
|
||||
* address in GS. That makes an attack harder, but still
|
||||
* possible if there's no SMAP protection.
|
||||
*/
|
||||
if (!smap_works_speculatively()) {
|
||||
/*
|
||||
* Mitigation can be provided from SWAPGS itself or
|
||||
* PTI as the CR3 write in the Meltdown mitigation
|
||||
* is serializing.
|
||||
*
|
||||
* If neither is there, mitigate with an LFENCE to
|
||||
* stop speculation through swapgs.
|
||||
*/
|
||||
if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
|
||||
!boot_cpu_has(X86_FEATURE_PTI))
|
||||
setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
|
||||
|
||||
/*
|
||||
* Enable lfences in the kernel entry (non-swapgs)
|
||||
* paths, to prevent user entry from speculatively
|
||||
* skipping swapgs.
|
||||
*/
|
||||
setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
|
||||
}
|
||||
}
|
||||
|
||||
pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
|
||||
}
|
||||
|
||||
static int __init nospectre_v1_cmdline(char *str)
|
||||
{
|
||||
spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
|
||||
return 0;
|
||||
}
|
||||
early_param("nospectre_v1", nospectre_v1_cmdline);
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "Spectre V2 : " fmt
|
||||
|
||||
@ -1290,7 +1377,7 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
|
||||
break;
|
||||
|
||||
case X86_BUG_SPECTRE_V1:
|
||||
return sprintf(buf, "Mitigation: __user pointer sanitization\n");
|
||||
return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
|
||||
|
||||
case X86_BUG_SPECTRE_V2:
|
||||
return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
|
||||
|
||||
@ -1022,6 +1022,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
|
||||
#define NO_L1TF BIT(3)
|
||||
#define NO_MDS BIT(4)
|
||||
#define MSBDS_ONLY BIT(5)
|
||||
#define NO_SWAPGS BIT(6)
|
||||
|
||||
#define VULNWL(_vendor, _family, _model, _whitelist) \
|
||||
{ X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
|
||||
@ -1048,30 +1049,38 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
|
||||
VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION),
|
||||
VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION),
|
||||
|
||||
VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY),
|
||||
VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY),
|
||||
VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY),
|
||||
VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY),
|
||||
VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY),
|
||||
VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY),
|
||||
VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
|
||||
VULNWL_INTEL(CORE_YONAH, NO_SSB),
|
||||
|
||||
VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY),
|
||||
VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
|
||||
|
||||
VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF),
|
||||
VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF),
|
||||
VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF),
|
||||
VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS),
|
||||
VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS),
|
||||
|
||||
/*
|
||||
* Technically, swapgs isn't serializing on AMD (despite it previously
|
||||
* being documented as such in the APM). But according to AMD, %gs is
|
||||
* updated non-speculatively, and the issuing of %gs-relative memory
|
||||
* operands will be blocked until the %gs update completes, which is
|
||||
* good enough for our purposes.
|
||||
*/
|
||||
|
||||
/* AMD Family 0xf - 0x12 */
|
||||
VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
|
||||
VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
|
||||
VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
|
||||
VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
|
||||
VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS),
|
||||
VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS),
|
||||
VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS),
|
||||
VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS),
|
||||
|
||||
/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
|
||||
VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS),
|
||||
VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS),
|
||||
VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS),
|
||||
VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS),
|
||||
{}
|
||||
};
|
||||
|
||||
@ -1108,6 +1117,9 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
|
||||
setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
|
||||
}
|
||||
|
||||
if (!cpu_matches(NO_SWAPGS))
|
||||
setup_force_cpu_bug(X86_BUG_SWAPGS);
|
||||
|
||||
if (cpu_matches(NO_MELTDOWN))
|
||||
return;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user