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https://github.com/edk2-porting/linux-next.git
synced 2024-11-19 16:14:13 +08:00
drm: Use spread spectrum when the bios tells us it's ok.
Lifted from the DDX modesetting. Signed-off-by: Kristian Høgsberg <krh@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
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43565a0648
@ -184,6 +184,8 @@ typedef struct drm_i915_private {
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unsigned int lvds_dither:1;
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unsigned int lvds_vbt:1;
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unsigned int int_crt_support:1;
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unsigned int lvds_use_ssc:1;
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int lvds_ssc_freq;
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struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
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int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
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@ -135,6 +135,14 @@ parse_general_features(struct drm_i915_private *dev_priv,
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if (general) {
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dev_priv->int_tv_support = general->int_tv_support;
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dev_priv->int_crt_support = general->int_crt_support;
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dev_priv->lvds_use_ssc = general->enable_ssc;
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if (dev_priv->lvds_use_ssc) {
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if (IS_I855(dev_priv->dev))
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dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
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else
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dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
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}
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}
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}
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@ -217,7 +217,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
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return false;
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}
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#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
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#define INTELPllInvalid(s) do { DRM_DEBUG(s); return false; } while (0)
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/**
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* Returns whether the given set of divisors are valid for a given refclk with
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* the given connectors.
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@ -726,7 +726,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
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int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
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int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
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int refclk;
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int refclk, num_outputs = 0;
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intel_clock_t clock;
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u32 dpll = 0, fp = 0, dspcntr, pipeconf;
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bool ok, is_sdvo = false, is_dvo = false;
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@ -763,9 +763,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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is_crt = true;
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break;
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}
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num_outputs++;
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}
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if (IS_I9XX(dev)) {
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if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
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refclk = dev_priv->lvds_ssc_freq * 1000;
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DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
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} else if (IS_I9XX(dev)) {
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refclk = 96000;
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} else {
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refclk = 48000;
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@ -824,11 +829,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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if (is_tv) {
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if (is_sdvo && is_tv)
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (is_tv)
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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}
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else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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