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https://github.com/edk2-porting/linux-next.git
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clk: samsung: exynos5420: update clocks for DISP1 block
This patch corrects some child-parent clock relationships, and updates the clocks according to the latest datasheet. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This commit is contained in:
Shaik Ameer Basha
Tomasz Figa
parent
3fac5941da
commit
424b673a05
@ -61,7 +61,8 @@
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#define SRC_TOP10 0x10280
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#define SRC_TOP11 0x10284
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#define SRC_TOP12 0x10288
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#define SRC_MASK_DISP10 0x1032c
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#define SRC_MASK_TOP2 0x10308
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#define SRC_MASK_DISP10 0x1032c
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#define SRC_MASK_FSYS 0x10340
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#define SRC_MASK_PERIC0 0x10350
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#define SRC_MASK_PERIC1 0x10354
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@ -100,6 +101,7 @@
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#define GATE_TOP_SCLK_MAU 0x1083c
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#define GATE_TOP_SCLK_FSYS 0x10840
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#define GATE_TOP_SCLK_PERIC 0x10850
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#define TOP_SPARE2 0x10b08
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#define BPLL_LOCK 0x20010
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#define BPLL_CON0 0x20110
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#define SRC_CDREX 0x20200
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@ -146,6 +148,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
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SRC_TOP10,
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SRC_TOP11,
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SRC_TOP12,
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SRC_MASK_TOP2,
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SRC_MASK_DISP10,
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SRC_MASK_FSYS,
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SRC_MASK_PERIC0,
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@ -186,6 +189,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
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GATE_TOP_SCLK_MAU,
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GATE_TOP_SCLK_FSYS,
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GATE_TOP_SCLK_PERIC,
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TOP_SPARE2,
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SRC_CDREX,
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SRC_KFC,
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DIV_KFC0,
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@ -252,6 +256,7 @@ PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
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PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
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PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
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PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
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PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
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PNAME(mout_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" };
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@ -271,7 +276,7 @@ PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
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PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
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PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
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PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
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PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
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PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
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PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
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@ -293,7 +298,9 @@ PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
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PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
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PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
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PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
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PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
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PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
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PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
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PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
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@ -368,6 +375,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
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MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
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MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
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MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
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MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
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MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
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@ -379,7 +387,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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SRC_TOP3, 0, 1),
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MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
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SRC_TOP3, 4, 1),
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MUX(0, "mout_aclk200_disp1", mout_aclk200_disp1_p, SRC_TOP3, 8, 1),
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MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
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SRC_TOP3, 8, 1),
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MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
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SRC_TOP3, 12, 1),
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MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
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@ -398,6 +407,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
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MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
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MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
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SRC_TOP5, 0, 1),
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MUX(0, "mout_aclk66_psgen", mout_aclk66_peric_p, SRC_TOP5, 4, 1),
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MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
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SRC_TOP5, 8, 1),
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@ -442,6 +453,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
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MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
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MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
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SRC_TOP12, 4, 1),
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MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
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SRC_TOP12, 8, 1),
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MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
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@ -460,6 +473,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
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MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
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MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
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MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
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MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
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/* MAU Block */
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MUX(0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
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@ -523,15 +538,16 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
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DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
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DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
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DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
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DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
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DIV_TOP2, 24, 3, "aclk300_disp1"),
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DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
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DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
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/* DISP1 Block */
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DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
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DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
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DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
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DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
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DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
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DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
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DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
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/* Audio Block */
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DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
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@ -647,6 +663,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
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GATE_BUS_TOP, 16, 0, 0),
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GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
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GATE_BUS_TOP, 17, 0, 0),
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GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
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GATE_BUS_TOP, 18, 0, 0),
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GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
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SRC_MASK_TOP2, 24, 0, 0),
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/* sclk */
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GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
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@ -696,15 +717,15 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
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/* Display */
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GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
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GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
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GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
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GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
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GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
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GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
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GATE_TOP_SCLK_DISP1, 9, 0, 0),
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GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
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GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
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GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
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GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
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GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
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/* Maudio Block */
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GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
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@ -833,10 +854,14 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
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GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
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GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
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GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
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GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
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GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
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GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
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GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
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0),
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GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
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GATE_IP_DISP1, 7, 0, 0),
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GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
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GATE_IP_DISP1, 8, 0, 0),
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GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
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GATE_IP_DISP1, 9, 0, 0),
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/* ISP */
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GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
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@ -867,9 +892,6 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
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GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
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GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
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GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
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GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
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0),
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};
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static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
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@ -140,7 +140,8 @@
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#define CLK_HDMI 413
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#define CLK_ACLK300_DISP1 420
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#define CLK_FIMD1 421
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#define CLK_SMMU_FIMD1 422
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#define CLK_SMMU_FIMD1M0 422
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#define CLK_SMMU_FIMD1M1 423
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#define CLK_ACLK166 430
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#define CLK_MIXER 431
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#define CLK_ACLK266 440
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