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clk: meson: meson8b: add the VPU clock trees
The VPU clock tree is slightly different on all three supported SoCs: Meson8 only has an input mux (which chooses between "fclk_div4", "fclk_div3", "fclk_div5" and "fclk_div7"), a divider and a gate. Meson8b has two VPU clock trees, each with an input mux (using the same parents as the input mux on Meson8), divider and a gates. The final VPU clock is a glitch-free mux which chooses between VPU_1 and VPU_2. Meson8m2 uses a similar clock tree as Meson8b but the last input clock is different: instead of using "fclk_div7" as input Meson8m2 uses "gp_pll". This was probably done in hardware to improve the accuracy of the clock because fclk_div7 gives us 2550MHz / 7 = 364.286MHz while GP_PLL can achieve 364.0MHz. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190324151104.18397-5-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl
Neil Armstrong
parent
b882964b37
commit
41785ce562
@ -1761,6 +1761,147 @@ static struct clk_regmap meson8m2_gp_pll = {
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},
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};
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static const char * const mmeson8b_vpu_0_1_parent_names[] = {
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"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
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};
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static const char * const mmeson8m2_vpu_0_1_parent_names[] = {
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"fclk_div4", "fclk_div3", "fclk_div5", "gp_pll"
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};
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static struct clk_regmap meson8b_vpu_0_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VPU_CLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu_0_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = mmeson8b_vpu_0_1_parent_names,
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.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8m2_vpu_0_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VPU_CLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu_0_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = mmeson8m2_vpu_0_1_parent_names,
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.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vpu_0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VPU_CLK_CNTL,
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.shift = 0,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu_0_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vpu_0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vpu_0 = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VPU_CLK_CNTL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vpu_0",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vpu_0_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vpu_1_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VPU_CLK_CNTL,
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.mask = 0x3,
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.shift = 25,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu_1_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = mmeson8b_vpu_0_1_parent_names,
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.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8m2_vpu_1_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VPU_CLK_CNTL,
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.mask = 0x3,
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.shift = 25,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu_1_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = mmeson8m2_vpu_0_1_parent_names,
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.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vpu_1_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VPU_CLK_CNTL,
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.shift = 16,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu_1_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vpu_1_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vpu_1 = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VPU_CLK_CNTL,
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.bit_idx = 24,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vpu_1",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "vpu_1_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap meson8b_vpu = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VPU_CLK_CNTL,
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.mask = 1,
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.shift = 31,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "vpu_0", "vpu_1" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_NO_REPARENT,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
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@ -2024,6 +2165,9 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
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[CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
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[CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
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[CLKID_MALI] = &meson8b_mali_0.hw,
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[CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
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[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
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[CLKID_VPU] = &meson8b_vpu_0.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -2210,6 +2354,13 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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[CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
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[CLKID_MALI_1] = &meson8b_mali_1.hw,
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[CLKID_MALI] = &meson8b_mali.hw,
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[CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
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[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
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[CLKID_VPU_0] = &meson8b_vpu_0.hw,
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[CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
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[CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
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[CLKID_VPU_1] = &meson8b_vpu_1.hw,
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[CLKID_VPU] = &meson8b_vpu.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -2398,6 +2549,13 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
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[CLKID_MALI] = &meson8b_mali.hw,
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[CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
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[CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
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[CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
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[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
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[CLKID_VPU_0] = &meson8b_vpu_0.hw,
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[CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
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[CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
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[CLKID_VPU_1] = &meson8b_vpu_1.hw,
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[CLKID_VPU] = &meson8b_vpu.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -2562,6 +2720,15 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
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&meson8b_mali,
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&meson8m2_gp_pll_dco,
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&meson8m2_gp_pll,
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&meson8b_vpu_0_sel,
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&meson8m2_vpu_0_sel,
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&meson8b_vpu_0_div,
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&meson8b_vpu_0,
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&meson8b_vpu_1_sel,
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&meson8m2_vpu_1_sel,
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&meson8b_vpu_1_div,
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&meson8b_vpu_1,
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&meson8b_vpu,
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};
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static const struct meson8b_clk_reset_line {
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@ -35,6 +35,7 @@
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#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
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#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
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#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
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#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
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#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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@ -149,8 +150,14 @@
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#define CLKID_MALI_1 180
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#define CLKID_GP_PLL_DCO 181
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#define CLKID_GP_PLL 182
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#define CLKID_VPU_0_SEL 183
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#define CLKID_VPU_0_DIV 184
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#define CLKID_VPU_0 185
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#define CLKID_VPU_1_SEL 186
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#define CLKID_VPU_1_DIV 187
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#define CLKID_VPU_1 189
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#define CLK_NR_CLKS 183
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#define CLK_NR_CLKS 191
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/*
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* include the CLKID and RESETID that have
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