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https://github.com/edk2-porting/linux-next.git
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[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common
use. They are built by __BUILD_BLAST_CACHE_RANGE().
Use protected_cache_op() macro for various protected_ routines.
Output code should be logically same.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
parent
6307751989
commit
41700e7399
@ -471,61 +471,29 @@ struct flush_icache_range_args {
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static inline void local_r4k_flush_icache_range(void *args)
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{
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struct flush_icache_range_args *fir_args = args;
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unsigned long dc_lsize = cpu_dcache_line_size();
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unsigned long ic_lsize = cpu_icache_line_size();
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unsigned long sc_lsize = cpu_scache_line_size();
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unsigned long start = fir_args->start;
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unsigned long end = fir_args->end;
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unsigned long addr, aend;
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if (!cpu_has_ic_fills_f_dc) {
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if (end - start > dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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addr = start & ~(dc_lsize - 1);
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aend = (end - 1) & ~(dc_lsize - 1);
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while (1) {
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/* Hit_Writeback_Inv_D */
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protected_writeback_dcache_line(addr);
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if (addr == aend)
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break;
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addr += dc_lsize;
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}
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protected_blast_dcache_range(start, end);
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}
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if (!cpu_icache_snoops_remote_store) {
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if (end - start > scache_size) {
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if (end - start > scache_size)
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r4k_blast_scache();
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} else {
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addr = start & ~(sc_lsize - 1);
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aend = (end - 1) & ~(sc_lsize - 1);
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while (1) {
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/* Hit_Writeback_Inv_SD */
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protected_writeback_scache_line(addr);
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if (addr == aend)
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break;
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addr += sc_lsize;
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}
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}
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else
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protected_blast_scache_range(start, end);
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}
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}
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if (end - start > icache_size)
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r4k_blast_icache();
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else {
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addr = start & ~(ic_lsize - 1);
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aend = (end - 1) & ~(ic_lsize - 1);
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while (1) {
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/* Hit_Invalidate_I */
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protected_flush_icache_line(addr);
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if (addr == aend)
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break;
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addr += ic_lsize;
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}
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}
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else
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protected_blast_icache_range(start, end);
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}
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static void r4k_flush_icache_range(unsigned long start, unsigned long end)
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@ -619,27 +587,14 @@ static void r4k_flush_icache_page(struct vm_area_struct *vma,
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static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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/* Catch bad driver code */
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BUG_ON(size == 0);
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if (cpu_has_subset_pcaches) {
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unsigned long sc_lsize = cpu_scache_line_size();
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if (size >= scache_size) {
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if (size >= scache_size)
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r4k_blast_scache();
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return;
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}
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a = addr & ~(sc_lsize - 1);
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end = (addr + size - 1) & ~(sc_lsize - 1);
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while (1) {
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flush_scache_line(a); /* Hit_Writeback_Inv_SD */
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if (a == end)
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break;
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a += sc_lsize;
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}
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else
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blast_scache_range(addr, addr + size);
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return;
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}
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@ -651,17 +606,8 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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if (size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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unsigned long dc_lsize = cpu_dcache_line_size();
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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break;
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a += dc_lsize;
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}
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blast_dcache_range(addr, addr + size);
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}
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bc_wback_inv(addr, size);
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@ -669,44 +615,22 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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/* Catch bad driver code */
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BUG_ON(size == 0);
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if (cpu_has_subset_pcaches) {
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unsigned long sc_lsize = cpu_scache_line_size();
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if (size >= scache_size) {
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if (size >= scache_size)
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r4k_blast_scache();
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return;
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}
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a = addr & ~(sc_lsize - 1);
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end = (addr + size - 1) & ~(sc_lsize - 1);
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while (1) {
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flush_scache_line(a); /* Hit_Writeback_Inv_SD */
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if (a == end)
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break;
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a += sc_lsize;
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}
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else
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blast_scache_range(addr, addr + size);
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return;
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}
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if (size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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unsigned long dc_lsize = cpu_dcache_line_size();
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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break;
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a += dc_lsize;
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}
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blast_dcache_range(addr, addr + size);
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}
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bc_inv(addr, size);
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@ -44,8 +44,6 @@ __asm__ __volatile__( \
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/* TX39H-style cache flush routines. */
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static void tx39h_flush_icache_all(void)
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{
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unsigned long start = KSEG0;
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unsigned long end = (start + icache_size);
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unsigned long flags, config;
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/* disable icache (set ICE#) */
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@ -53,33 +51,18 @@ static void tx39h_flush_icache_all(void)
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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/* invalidate icache */
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while (start < end) {
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cache16_unroll32(start, Index_Invalidate_I);
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start += 0x200;
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}
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blast_icache16();
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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/* Catch bad driver code */
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BUG_ON(size == 0);
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iob();
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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while (1) {
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invalidate_dcache_line(a); /* Hit_Invalidate_D */
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if (a == end) break;
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a += dc_lsize;
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}
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blast_inv_dcache_range(addr, addr + size);
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}
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@ -241,42 +224,21 @@ static void tx39_flush_data_cache_page(unsigned long addr)
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static void tx39_flush_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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unsigned long addr, aend;
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if (end - start > dcache_size)
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tx39_blast_dcache();
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else {
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addr = start & ~(dc_lsize - 1);
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aend = (end - 1) & ~(dc_lsize - 1);
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while (1) {
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/* Hit_Writeback_Inv_D */
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protected_writeback_dcache_line(addr);
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if (addr == aend)
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break;
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addr += dc_lsize;
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}
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}
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else
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protected_blast_dcache_range(start, end);
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if (end - start > icache_size)
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tx39_blast_icache();
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else {
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unsigned long flags, config;
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addr = start & ~(dc_lsize - 1);
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aend = (end - 1) & ~(dc_lsize - 1);
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/* disable icache (set ICE#) */
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local_irq_save(flags);
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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while (1) {
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/* Hit_Invalidate_I */
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protected_flush_icache_line(addr);
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if (addr == aend)
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break;
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addr += dc_lsize;
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}
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protected_blast_icache_range(start, end);
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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@ -311,7 +273,7 @@ static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page
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static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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unsigned long end;
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if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
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end = addr + size;
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@ -322,20 +284,13 @@ static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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} else if (size > dcache_size) {
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tx39_blast_dcache();
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} else {
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end) break;
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a += dc_lsize;
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}
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blast_dcache_range(addr, addr + size);
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}
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}
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static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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unsigned long end;
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if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
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end = addr + size;
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@ -346,14 +301,7 @@ static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
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} else if (size > dcache_size) {
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tx39_blast_dcache();
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} else {
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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while (1) {
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invalidate_dcache_line(a); /* Hit_Invalidate_D */
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if (a == end) break;
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a += dc_lsize;
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}
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blast_inv_dcache_range(addr, addr + size);
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}
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}
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@ -14,6 +14,7 @@
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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#include <asm/cpu-features.h>
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/*
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* This macro return a properly sign-extended address suitable as base address
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@ -78,22 +79,25 @@ static inline void flush_scache_line(unsigned long addr)
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cache_op(Hit_Writeback_Inv_SD, addr);
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}
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#define protected_cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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"1: cache %0, (%1) \n" \
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"2: .set pop \n" \
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" .section __ex_table,\"a\" \n" \
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" "STR(PTR)" 1b, 2b \n" \
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" .previous" \
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: \
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: "i" (op), "r" (addr))
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/*
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* The next two are for badland addresses like signal trampolines.
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*/
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set mips3 \n"
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"1: cache %0, (%1) \n"
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"2: .set pop \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 2b \n"
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" .previous"
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:
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: "i" (Hit_Invalidate_I), "r" (addr));
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protected_cache_op(Hit_Invalidate_I, addr);
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}
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/*
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@ -104,32 +108,12 @@ static inline void protected_flush_icache_line(unsigned long addr)
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set mips3 \n"
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"1: cache %0, (%1) \n"
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"2: .set pop \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 2b \n"
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" .previous"
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:
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: "i" (Hit_Writeback_Inv_D), "r" (addr));
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protected_cache_op(Hit_Writeback_Inv_D, addr);
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}
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static inline void protected_writeback_scache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set mips3 \n"
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"1: cache %0, (%1) \n"
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"2: .set pop \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 2b \n"
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" .previous"
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:
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: "i" (Hit_Writeback_Inv_SD), "r" (addr));
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protected_cache_op(Hit_Writeback_Inv_SD, addr);
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}
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/*
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@ -295,4 +279,28 @@ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
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/* build blast_xxx_range, protected_blast_xxx_range */
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#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
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static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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while (1) { \
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prot##cache_op(hitop, addr); \
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if (addr == aend) \
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break; \
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addr += lsize; \
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} \
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}
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
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/* blast_inv_dcache_range */
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__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
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#endif /* _ASM_R4KCACHE_H */
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