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sata_mv: cosmetic preparations for IRQ coalescing
Various cosmetic changes in preparation for the IRQ coalescing feature. Note that the various MV_IRQ_COAL_* definitions are restored/renamed in the folloup patch which adds IRQ coalescing to the driver. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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@ -1,10 +1,13 @@
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/*
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* sata_mv.c - Marvell SATA support
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*
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* Copyright 2008: Marvell Corporation, all rights reserved.
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* Copyright 2008-2009: Marvell Corporation, all rights reserved.
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* Copyright 2005: EMC Corporation, all rights reserved.
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* Copyright 2005 Red Hat, Inc. All rights reserved.
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*
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* Originally written by Brett Russ.
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* Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
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*
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* Please ALWAYS copy linux-ide@vger.kernel.org on emails.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -25,8 +28,6 @@
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/*
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* sata_mv TODO list:
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*
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* --> Errata workaround for NCQ device errors.
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*
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* --> More errata workarounds for PCI-X.
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*
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* --> Complete a full errata audit for all chipsets to identify others.
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@ -68,6 +69,16 @@
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#define DRV_NAME "sata_mv"
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#define DRV_VERSION "1.26"
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/*
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* module options
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*/
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static int msi;
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#ifdef CONFIG_PCI
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module_param(msi, int, S_IRUGO);
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MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
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#endif
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enum {
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/* BAR's are enumerated in terms of pci_resource_start() terms */
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MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
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@ -78,12 +89,6 @@ enum {
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MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
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MV_PCI_REG_BASE = 0,
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MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
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MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
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MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
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MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
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MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
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MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
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MV_SATAHC0_REG_BASE = 0x20000,
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MV_FLASH_CTL_OFS = 0x1046c,
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@ -115,16 +120,14 @@ enum {
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/* Host Flags */
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MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
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MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
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MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
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MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
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MV_GEN_II_FLAGS = MV_COMMON_FLAGS | MV_FLAG_IRQ_COALESCE |
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ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
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ATA_FLAG_NCQ,
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MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
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ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
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MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
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@ -179,16 +182,16 @@ enum {
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PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
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SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
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SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
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ERR_IRQ = (1 << 0), /* shift by port # */
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DONE_IRQ = (1 << 1), /* shift by port # */
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ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
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DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
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HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
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HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
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PCI_ERR = (1 << 18),
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TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
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TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
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PORTS_0_3_COAL_DONE = (1 << 8),
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PORTS_4_7_COAL_DONE = (1 << 17),
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PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
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TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
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TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
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PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
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PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
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ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
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GPIO_INT = (1 << 22),
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SELF_INT = (1 << 23),
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TWSI_INT = (1 << 24),
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@ -621,7 +624,7 @@ static struct ata_port_operations mv6_ops = {
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.softreset = mv_softreset,
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.error_handler = mv_pmp_error_handler,
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.sff_check_status = mv_sff_check_status,
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.sff_check_status = mv_sff_check_status,
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.sff_irq_clear = mv_sff_irq_clear,
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.check_atapi_dma = mv_check_atapi_dma,
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.bmdma_setup = mv_bmdma_setup,
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@ -1255,8 +1258,8 @@ static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
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}
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/**
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* mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
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* @ap: Port being initialized
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* mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
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* @ap: Port being initialized
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*
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* There are two DMA modes on these chips: basic DMA, and EDMA.
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*
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@ -2000,7 +2003,7 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
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struct mv_host_priv *hpriv = ap->host->private_data;
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/*
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* Workaround for 88SX60x1 FEr SATA#25 (part 2).
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*
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*
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* After any NCQ error, the READ_LOG_EXT command
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* from libata-eh *must* use mv_qc_issue_fis().
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* Otherwise it might fail, due to chip errata.
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@ -3704,12 +3707,6 @@ static struct pci_driver mv_pci_driver = {
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.remove = ata_pci_remove_one,
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};
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/*
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* module options
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*/
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static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
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/* move to PCI layer or libata core? */
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static int pci_go_64(struct pci_dev *pdev)
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{
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@ -3891,10 +3888,5 @@ MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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MODULE_ALIAS("platform:" DRV_NAME);
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#ifdef CONFIG_PCI
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module_param(msi, int, 0444);
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MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
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#endif
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module_init(mv_init);
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module_exit(mv_exit);
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