mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-15 16:53:54 +08:00
MIPS: Add uprobes support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
e3b28831c1
commit
40e084a506
@ -1,6 +1,7 @@
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config MIPS
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bool
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default y
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select ARCH_SUPPORTS_UPROBES
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select ARCH_MIGHT_HAVE_PC_PARPORT
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select ARCH_MIGHT_HAVE_PC_SERIO
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select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
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@ -1041,6 +1042,9 @@ config FW_CFE
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config ARCH_DMA_ADDR_T_64BIT
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def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
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config ARCH_SUPPORTS_UPROBES
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bool
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config DMA_MAYBE_COHERENT
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select DMA_NONCOHERENT
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bool
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@ -11,7 +11,9 @@ enum die_val {
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DIE_PAGE_FAULT,
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DIE_BREAK,
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DIE_SSTEPBP,
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DIE_MSAFP
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DIE_MSAFP,
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DIE_UPROBE,
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DIE_UPROBE_XOL,
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};
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#endif /* _ASM_MIPS_KDEBUG_H */
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@ -14,11 +14,16 @@
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#include <linux/linkage.h>
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#include <linux/types.h>
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#include <asm/isadep.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#include <uapi/asm/ptrace.h>
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/*
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* This struct defines the way the registers are stored on the stack during a
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* system call/exception. As usual the registers k0/k1 aren't being saved.
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*
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* If you add a register here, also add it to regoffset_table[] in
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* arch/mips/kernel/ptrace.c.
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*/
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struct pt_regs {
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#ifdef CONFIG_32BIT
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@ -43,8 +48,83 @@ struct pt_regs {
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unsigned long long mpl[6]; /* MTM{0-5} */
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unsigned long long mtp[6]; /* MTP{0-5} */
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#endif
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unsigned long __last[0];
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} __aligned(8);
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static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
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{
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return regs->regs[31];
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}
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/*
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* Don't use asm-generic/ptrace.h it defines FP accessors that don't make
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* sense on MIPS. We rather want an error if they get invoked.
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*/
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static inline void instruction_pointer_set(struct pt_regs *regs,
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unsigned long val)
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{
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regs->cp0_epc = val;
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}
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/* Query offset/name of register from its name/offset */
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extern int regs_query_register_offset(const char *name);
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#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
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/**
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* regs_get_register() - get register value from its offset
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* @regs: pt_regs from which register value is gotten.
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* @offset: offset number of the register.
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*
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* regs_get_register returns the value of a register. The @offset is the
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* offset of the register in struct pt_regs address which specified by @regs.
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* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
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*/
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static inline unsigned long regs_get_register(struct pt_regs *regs,
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unsigned int offset)
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{
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if (unlikely(offset > MAX_REG_OFFSET))
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return 0;
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return *(unsigned long *)((unsigned long)regs + offset);
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}
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/**
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* regs_within_kernel_stack() - check the address in the stack
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* @regs: pt_regs which contains kernel stack pointer.
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* @addr: address which is checked.
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*
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* regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
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* If @addr is within the kernel stack, it returns true. If not, returns false.
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*/
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static inline int regs_within_kernel_stack(struct pt_regs *regs,
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unsigned long addr)
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{
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return ((addr & ~(THREAD_SIZE - 1)) ==
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(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
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}
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/**
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* regs_get_kernel_stack_nth() - get Nth entry of the stack
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* @regs: pt_regs which contains kernel stack pointer.
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* @n: stack entry number.
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*
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* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
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* is specified by @regs. If the @n th entry is NOT in the kernel stack,
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* this returns 0.
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*/
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static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
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unsigned int n)
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{
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unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
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addr += n;
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if (regs_within_kernel_stack(regs, (unsigned long)addr))
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return *addr;
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else
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return 0;
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}
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struct task_struct;
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extern int ptrace_getregs(struct task_struct *child,
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@ -99,6 +99,7 @@ static inline struct thread_info *current_thread_info(void)
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#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */
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#define TIF_SECCOMP 4 /* secure computing */
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#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
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#define TIF_UPROBE 6 /* breakpointed or singlestepping */
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#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
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#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
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#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
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@ -122,6 +123,7 @@ static inline struct thread_info *current_thread_info(void)
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#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
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#define _TIF_SECCOMP (1<<TIF_SECCOMP)
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#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
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#define _TIF_UPROBE (1<<TIF_UPROBE)
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#define _TIF_USEDFPU (1<<TIF_USEDFPU)
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#define _TIF_NOHZ (1<<TIF_NOHZ)
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#define _TIF_FIXADE (1<<TIF_FIXADE)
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@ -146,7 +148,8 @@ static inline struct thread_info *current_thread_info(void)
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/* work to do on interrupt/exception return */
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#define _TIF_WORK_MASK \
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(_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
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(_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME | \
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_TIF_UPROBE)
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/* work to do on any return to u-space */
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#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
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_TIF_WORK_SYSCALL_EXIT | \
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58
arch/mips/include/asm/uprobes.h
Normal file
58
arch/mips/include/asm/uprobes.h
Normal file
@ -0,0 +1,58 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_UPROBES_H
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#define __ASM_UPROBES_H
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#include <linux/notifier.h>
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#include <linux/types.h>
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#include <asm/break.h>
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#include <asm/inst.h>
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/*
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* We want this to be defined as union mips_instruction but that makes the
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* generic code blow up.
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*/
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typedef u32 uprobe_opcode_t;
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/*
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* Classic MIPS (note this implementation doesn't consider microMIPS yet)
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* instructions are always 4 bytes but in order to deal with branches and
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* their delay slots, we treat instructions as having 8 bytes maximum.
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*/
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#define MAX_UINSN_BYTES 8
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#define UPROBE_XOL_SLOT_BYTES 128 /* Max. cache line size */
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#define UPROBE_BRK_UPROBE 0x000d000d /* break 13 */
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#define UPROBE_BRK_UPROBE_XOL 0x000e000d /* break 14 */
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#define UPROBE_SWBP_INSN UPROBE_BRK_UPROBE
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#define UPROBE_SWBP_INSN_SIZE 4
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struct arch_uprobe {
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unsigned long resume_epc;
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u32 insn[2];
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u32 ixol[2];
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union mips_instruction orig_inst[MAX_UINSN_BYTES / 4];
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};
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struct arch_uprobe_task {
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unsigned long saved_trap_nr;
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};
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extern int arch_uprobe_analyze_insn(struct arch_uprobe *aup,
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struct mm_struct *mm, unsigned long addr);
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extern int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs);
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extern int arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs);
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extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk);
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extern int arch_uprobe_exception_notify(struct notifier_block *self,
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unsigned long val, void *data);
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extern void arch_uprobe_abort_xol(struct arch_uprobe *aup,
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struct pt_regs *regs);
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extern unsigned long arch_uretprobe_hijack_return_addr(
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unsigned long trampoline_vaddr, struct pt_regs *regs);
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#endif /* __ASM_UPROBES_H */
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@ -21,6 +21,8 @@
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#define BRK_DIVZERO 7 /* Divide by zero check */
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#define BRK_RANGE 8 /* Range error check */
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#define BRK_BUG 12 /* Used by BUG() */
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#define BRK_UPROBE 13 /* See <asm/uprobes.h> */
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#define BRK_UPROBE_XOL 14 /* See <asm/uprobes.h> */
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#define BRK_MEMU 514 /* Used by FPU emulator */
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#define BRK_KPROBE_BP 515 /* Kprobe break */
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#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */
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@ -100,6 +100,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
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obj-$(CONFIG_JUMP_LABEL) += jump_label.o
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obj-$(CONFIG_UPROBES) += uprobes.o
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obj-$(CONFIG_MIPS_CM) += mips-cm.o
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obj-$(CONFIG_MIPS_CPC) += mips-cpc.o
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@ -25,6 +25,7 @@
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#include <linux/regset.h>
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#include <linux/smp.h>
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#include <linux/security.h>
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#include <linux/stddef.h>
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#include <linux/tracehook.h>
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#include <linux/audit.h>
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#include <linux/seccomp.h>
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@ -490,6 +491,93 @@ enum mips_regset {
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REGSET_FPR,
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};
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struct pt_regs_offset {
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const char *name;
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int offset;
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};
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#define REG_OFFSET_NAME(reg, r) { \
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.name = #reg, \
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.offset = offsetof(struct pt_regs, r) \
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}
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#define REG_OFFSET_END { \
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.name = NULL, \
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.offset = 0 \
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}
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static const struct pt_regs_offset regoffset_table[] = {
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REG_OFFSET_NAME(r0, regs[0]),
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REG_OFFSET_NAME(r1, regs[1]),
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REG_OFFSET_NAME(r2, regs[2]),
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REG_OFFSET_NAME(r3, regs[3]),
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REG_OFFSET_NAME(r4, regs[4]),
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REG_OFFSET_NAME(r5, regs[5]),
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REG_OFFSET_NAME(r6, regs[6]),
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REG_OFFSET_NAME(r7, regs[7]),
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REG_OFFSET_NAME(r8, regs[8]),
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REG_OFFSET_NAME(r9, regs[9]),
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REG_OFFSET_NAME(r10, regs[10]),
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REG_OFFSET_NAME(r11, regs[11]),
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REG_OFFSET_NAME(r12, regs[12]),
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REG_OFFSET_NAME(r13, regs[13]),
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REG_OFFSET_NAME(r14, regs[14]),
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REG_OFFSET_NAME(r15, regs[15]),
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REG_OFFSET_NAME(r16, regs[16]),
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REG_OFFSET_NAME(r17, regs[17]),
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REG_OFFSET_NAME(r18, regs[18]),
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REG_OFFSET_NAME(r19, regs[19]),
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REG_OFFSET_NAME(r20, regs[20]),
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REG_OFFSET_NAME(r21, regs[21]),
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REG_OFFSET_NAME(r22, regs[22]),
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REG_OFFSET_NAME(r23, regs[23]),
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REG_OFFSET_NAME(r24, regs[24]),
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REG_OFFSET_NAME(r25, regs[25]),
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REG_OFFSET_NAME(r26, regs[26]),
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REG_OFFSET_NAME(r27, regs[27]),
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REG_OFFSET_NAME(r28, regs[28]),
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REG_OFFSET_NAME(r29, regs[29]),
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REG_OFFSET_NAME(r30, regs[30]),
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REG_OFFSET_NAME(r31, regs[31]),
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REG_OFFSET_NAME(c0_status, cp0_status),
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REG_OFFSET_NAME(hi, hi),
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REG_OFFSET_NAME(lo, lo),
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#ifdef CONFIG_CPU_HAS_SMARTMIPS
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REG_OFFSET_NAME(acx, acx),
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#endif
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REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
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REG_OFFSET_NAME(c0_cause, cp0_cause),
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REG_OFFSET_NAME(c0_epc, cp0_epc),
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#ifdef CONFIG_MIPS_MT_SMTC
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REG_OFFSET_NAME(c0_tcstatus, cp0_tcstatus),
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#endif
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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REG_OFFSET_NAME(mpl0, mpl[0]),
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REG_OFFSET_NAME(mpl1, mpl[1]),
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REG_OFFSET_NAME(mpl2, mpl[2]),
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REG_OFFSET_NAME(mtp0, mtp[0]),
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REG_OFFSET_NAME(mtp1, mtp[1]),
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REG_OFFSET_NAME(mtp2, mtp[2]),
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#endif
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REG_OFFSET_END,
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};
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/**
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* regs_query_register_offset() - query register offset from its name
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* @name: the name of a register
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*
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* regs_query_register_offset() returns the offset of a register in struct
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* pt_regs from its name. If the name is invalid, this returns -EINVAL;
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*/
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int regs_query_register_offset(const char *name)
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{
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const struct pt_regs_offset *roff;
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for (roff = regoffset_table; roff->name != NULL; roff++)
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if (!strcmp(roff->name, name))
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return roff->offset;
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return -EINVAL;
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}
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#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
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static const struct user_regset mips_regsets[] = {
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@ -21,6 +21,7 @@
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#include <linux/wait.h>
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#include <linux/ptrace.h>
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#include <linux/unistd.h>
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#include <linux/uprobes.h>
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#include <linux/compiler.h>
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#include <linux/syscalls.h>
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#include <linux/uaccess.h>
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@ -856,6 +857,9 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
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user_exit();
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if (thread_info_flags & _TIF_UPROBE)
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uprobe_notify_resume(regs);
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/* deal with pending signal delivery */
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if (thread_info_flags & _TIF_SIGPENDING)
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do_signal(regs);
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@ -984,6 +984,18 @@ asmlinkage void do_bp(struct pt_regs *regs)
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* pertain to them.
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*/
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switch (bcode) {
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case BRK_UPROBE:
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if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
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current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
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goto out;
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else
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break;
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case BRK_UPROBE_XOL:
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if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
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current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
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goto out;
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else
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break;
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case BRK_KPROBE_BP:
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if (notify_die(DIE_BREAK, "debug", regs, bcode,
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current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
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341
arch/mips/kernel/uprobes.c
Normal file
341
arch/mips/kernel/uprobes.c
Normal file
@ -0,0 +1,341 @@
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#include <linux/highmem.h>
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#include <linux/kdebug.h>
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#include <linux/types.h>
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#include <linux/notifier.h>
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#include <linux/sched.h>
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#include <linux/uprobes.h>
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#include <asm/branch.h>
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#include <asm/cpu-features.h>
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#include <asm/ptrace.h>
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#include <asm/inst.h>
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static inline int insn_has_delay_slot(const union mips_instruction insn)
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{
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switch (insn.i_format.opcode) {
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/*
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* jr and jalr are in r_format format.
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*/
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case spec_op:
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switch (insn.r_format.func) {
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case jalr_op:
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case jr_op:
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return 1;
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}
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break;
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/*
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* This group contains:
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* bltz_op, bgez_op, bltzl_op, bgezl_op,
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* bltzal_op, bgezal_op, bltzall_op, bgezall_op.
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*/
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case bcond_op:
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switch (insn.i_format.rt) {
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case bltz_op:
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case bltzl_op:
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case bgez_op:
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case bgezl_op:
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case bltzal_op:
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case bltzall_op:
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case bgezal_op:
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case bgezall_op:
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case bposge32_op:
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return 1;
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}
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break;
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/*
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* These are unconditional and in j_format.
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*/
|
||||
case jal_op:
|
||||
case j_op:
|
||||
case beq_op:
|
||||
case beql_op:
|
||||
case bne_op:
|
||||
case bnel_op:
|
||||
case blez_op: /* not really i_format */
|
||||
case blezl_op:
|
||||
case bgtz_op:
|
||||
case bgtzl_op:
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* And now the FPA/cp1 branch instructions.
|
||||
*/
|
||||
case cop1_op:
|
||||
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
||||
case lwc2_op: /* This is bbit0 on Octeon */
|
||||
case ldc2_op: /* This is bbit032 on Octeon */
|
||||
case swc2_op: /* This is bbit1 on Octeon */
|
||||
case sdc2_op: /* This is bbit132 on Octeon */
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
|
||||
* @mm: the probed address space.
|
||||
* @arch_uprobe: the probepoint information.
|
||||
* @addr: virtual address at which to install the probepoint
|
||||
* Return 0 on success or a -ve number on error.
|
||||
*/
|
||||
int arch_uprobe_analyze_insn(struct arch_uprobe *aup,
|
||||
struct mm_struct *mm, unsigned long addr)
|
||||
{
|
||||
union mips_instruction inst;
|
||||
|
||||
/*
|
||||
* For the time being this also blocks attempts to use uprobes with
|
||||
* MIPS16 and microMIPS.
|
||||
*/
|
||||
if (addr & 0x03)
|
||||
return -EINVAL;
|
||||
|
||||
inst.word = aup->insn[0];
|
||||
aup->ixol[0] = aup->insn[insn_has_delay_slot(inst)];
|
||||
aup->ixol[1] = UPROBE_BRK_UPROBE_XOL; /* NOP */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* is_trap_insn - check if the instruction is a trap variant
|
||||
* @insn: instruction to be checked.
|
||||
* Returns true if @insn is a trap variant.
|
||||
*
|
||||
* This definition overrides the weak definition in kernel/events/uprobes.c.
|
||||
* and is needed for the case where an architecture has multiple trap
|
||||
* instructions (like PowerPC or MIPS). We treat BREAK just like the more
|
||||
* modern conditional trap instructions.
|
||||
*/
|
||||
bool is_trap_insn(uprobe_opcode_t *insn)
|
||||
{
|
||||
union mips_instruction inst;
|
||||
|
||||
inst.word = *insn;
|
||||
|
||||
switch (inst.i_format.opcode) {
|
||||
case spec_op:
|
||||
switch (inst.r_format.func) {
|
||||
case break_op:
|
||||
case teq_op:
|
||||
case tge_op:
|
||||
case tgeu_op:
|
||||
case tlt_op:
|
||||
case tltu_op:
|
||||
case tne_op:
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case bcond_op: /* Yes, really ... */
|
||||
switch (inst.u_format.rt) {
|
||||
case teqi_op:
|
||||
case tgei_op:
|
||||
case tgeiu_op:
|
||||
case tlti_op:
|
||||
case tltiu_op:
|
||||
case tnei_op:
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define UPROBE_TRAP_NR ULONG_MAX
|
||||
|
||||
/*
|
||||
* arch_uprobe_pre_xol - prepare to execute out of line.
|
||||
* @auprobe: the probepoint information.
|
||||
* @regs: reflects the saved user state of current task.
|
||||
*/
|
||||
int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs)
|
||||
{
|
||||
struct uprobe_task *utask = current->utask;
|
||||
union mips_instruction insn;
|
||||
|
||||
/*
|
||||
* Now find the EPC where to resume after the breakpoint has been
|
||||
* dealt with. This may require emulation of a branch.
|
||||
*/
|
||||
aup->resume_epc = regs->cp0_epc + 4;
|
||||
if (insn_has_delay_slot((union mips_instruction) aup->insn[0])) {
|
||||
unsigned long epc;
|
||||
|
||||
epc = regs->cp0_epc;
|
||||
__compute_return_epc_for_insn(regs, insn);
|
||||
aup->resume_epc = regs->cp0_epc;
|
||||
}
|
||||
|
||||
utask->autask.saved_trap_nr = current->thread.trap_nr;
|
||||
current->thread.trap_nr = UPROBE_TRAP_NR;
|
||||
regs->cp0_epc = current->utask->xol_vaddr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs)
|
||||
{
|
||||
struct uprobe_task *utask = current->utask;
|
||||
|
||||
current->thread.trap_nr = utask->autask.saved_trap_nr;
|
||||
regs->cp0_epc = aup->resume_epc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* If xol insn itself traps and generates a signal(Say,
|
||||
* SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
|
||||
* instruction jumps back to its own address. It is assumed that anything
|
||||
* like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
|
||||
*
|
||||
* arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
|
||||
* arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
|
||||
* UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
|
||||
*/
|
||||
bool arch_uprobe_xol_was_trapped(struct task_struct *tsk)
|
||||
{
|
||||
if (tsk->thread.trap_nr != UPROBE_TRAP_NR)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
int arch_uprobe_exception_notify(struct notifier_block *self,
|
||||
unsigned long val, void *data)
|
||||
{
|
||||
struct die_args *args = data;
|
||||
struct pt_regs *regs = args->regs;
|
||||
|
||||
/* regs == NULL is a kernel bug */
|
||||
if (WARN_ON(!regs))
|
||||
return NOTIFY_DONE;
|
||||
|
||||
/* We are only interested in userspace traps */
|
||||
if (!user_mode(regs))
|
||||
return NOTIFY_DONE;
|
||||
|
||||
switch (val) {
|
||||
case DIE_BREAK:
|
||||
if (uprobe_pre_sstep_notifier(regs))
|
||||
return NOTIFY_STOP;
|
||||
break;
|
||||
case DIE_UPROBE_XOL:
|
||||
if (uprobe_post_sstep_notifier(regs))
|
||||
return NOTIFY_STOP;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function gets called when XOL instruction either gets trapped or
|
||||
* the thread has a fatal signal. Reset the instruction pointer to its
|
||||
* probed address for the potential restart or for post mortem analysis.
|
||||
*/
|
||||
void arch_uprobe_abort_xol(struct arch_uprobe *aup,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
struct uprobe_task *utask = current->utask;
|
||||
|
||||
instruction_pointer_set(regs, utask->vaddr);
|
||||
}
|
||||
|
||||
unsigned long arch_uretprobe_hijack_return_addr(
|
||||
unsigned long trampoline_vaddr, struct pt_regs *regs)
|
||||
{
|
||||
unsigned long ra;
|
||||
|
||||
ra = regs->regs[31];
|
||||
|
||||
/* Replace the return address with the trampoline address */
|
||||
regs->regs[31] = ra;
|
||||
|
||||
return ra;
|
||||
}
|
||||
|
||||
/**
|
||||
* set_swbp - store breakpoint at a given address.
|
||||
* @auprobe: arch specific probepoint information.
|
||||
* @mm: the probed process address space.
|
||||
* @vaddr: the virtual address to insert the opcode.
|
||||
*
|
||||
* For mm @mm, store the breakpoint instruction at @vaddr.
|
||||
* Return 0 (success) or a negative errno.
|
||||
*
|
||||
* This version overrides the weak version in kernel/events/uprobes.c.
|
||||
* It is required to handle MIPS16 and microMIPS.
|
||||
*/
|
||||
int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
|
||||
unsigned long vaddr)
|
||||
{
|
||||
return uprobe_write_opcode(mm, vaddr, UPROBE_SWBP_INSN);
|
||||
}
|
||||
|
||||
/**
|
||||
* set_orig_insn - Restore the original instruction.
|
||||
* @mm: the probed process address space.
|
||||
* @auprobe: arch specific probepoint information.
|
||||
* @vaddr: the virtual address to insert the opcode.
|
||||
*
|
||||
* For mm @mm, restore the original opcode (opcode) at @vaddr.
|
||||
* Return 0 (success) or a negative errno.
|
||||
*
|
||||
* This overrides the weak version in kernel/events/uprobes.c.
|
||||
*/
|
||||
int set_orig_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
|
||||
unsigned long vaddr)
|
||||
{
|
||||
return uprobe_write_opcode(mm, vaddr,
|
||||
*(uprobe_opcode_t *)&auprobe->orig_inst[0].word);
|
||||
}
|
||||
|
||||
void __weak arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
|
||||
void *src, unsigned long len)
|
||||
{
|
||||
void *kaddr;
|
||||
|
||||
/* Initialize the slot */
|
||||
kaddr = kmap_atomic(page);
|
||||
memcpy(kaddr + (vaddr & ~PAGE_MASK), src, len);
|
||||
kunmap_atomic(kaddr);
|
||||
|
||||
/*
|
||||
* The MIPS version of flush_icache_range will operate safely on
|
||||
* user space addresses and more importantly, it doesn't require a
|
||||
* VMA argument.
|
||||
*/
|
||||
flush_icache_range(vaddr, vaddr + len);
|
||||
}
|
||||
|
||||
/**
|
||||
* uprobe_get_swbp_addr - compute address of swbp given post-swbp regs
|
||||
* @regs: Reflects the saved state of the task after it has hit a breakpoint
|
||||
* instruction.
|
||||
* Return the address of the breakpoint instruction.
|
||||
*
|
||||
* This overrides the weak version in kernel/events/uprobes.c.
|
||||
*/
|
||||
unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
|
||||
{
|
||||
return instruction_pointer(regs);
|
||||
}
|
||||
|
||||
/*
|
||||
* See if the instruction can be emulated.
|
||||
* Returns true if instruction was emulated, false otherwise.
|
||||
*
|
||||
* For now we always emulate so this function just returns 0.
|
||||
*/
|
||||
bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user