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i.MX device tree changes for 5.5:

Browse Source 
- New board support: Netronix E60K02 and Kobo Clara HD, Kontron N6311
    and N6411, OPOS6UL and OPOS6ULDev.
  - Correct speed grading fuse settings and add opp-suspend property for
    i.MX7D device tree.
  - Move usdhc clocks assignment from SoC to board level DTS for imx7ulp,
    and use APLL_PFD1 as usdhc's clock source on imx7ulp-evk board.
  - Add missing cooling device properties for CPUs for i.MX6/7 SoCs.
  - Add sensor GPIO regulator and assign power supplies for magnetometer
    for imx6ul-14x14-evk board.
  - Replace "simple-bus" with "simple-mfd" for ANATOP device for i.MX6/7
    SoCs.
  - Fix DTC W=1 warnings by not using simple-audio-card,dai-link on
    imx6qdl-gw551x and imx6q-gw54xx board.
  - Move to use DRM bindings for the Seiko 43WVF1G panel on imx53-qsb.
  - A series from Frieder Schrempf to support more i.MX6UL/ULL-based SoMs
    and boards from Kontron Electronics GmbH.
  - A few patches from Michal Vokáč to enable more devices support on
    imx6dl-yapp4 board.
  - A patch series from Philippe Schenker to improve i.MX6/7 Apalis and
    Colibri board support.
  - A patch series from Sébastien Szymanski to update i.MX6 APF6/APF6Dev
    device tree with more devices added and adopting DRM bindings for
    display.
  - Random improvements, clean-up and device additions on various boards.
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Merge tag 'imx-dt-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX device tree changes for 5.5:
 - New board support: Netronix E60K02 and Kobo Clara HD, Kontron N6311
   and N6411, OPOS6UL and OPOS6ULDev.
 - Correct speed grading fuse settings and add opp-suspend property for
   i.MX7D device tree.
 - Move usdhc clocks assignment from SoC to board level DTS for imx7ulp,
   and use APLL_PFD1 as usdhc's clock source on imx7ulp-evk board.
 - Add missing cooling device properties for CPUs for i.MX6/7 SoCs.
 - Add sensor GPIO regulator and assign power supplies for magnetometer
   for imx6ul-14x14-evk board.
 - Replace "simple-bus" with "simple-mfd" for ANATOP device for i.MX6/7
   SoCs.
 - Fix DTC W=1 warnings by not using simple-audio-card,dai-link on
   imx6qdl-gw551x and imx6q-gw54xx board.
 - Move to use DRM bindings for the Seiko 43WVF1G panel on imx53-qsb.
 - A series from Frieder Schrempf to support more i.MX6UL/ULL-based SoMs
   and boards from Kontron Electronics GmbH.
 - A few patches from Michal Vokáč to enable more devices support on
   imx6dl-yapp4 board.
 - A patch series from Philippe Schenker to improve i.MX6/7 Apalis and
   Colibri board support.
 - A patch series from Sébastien Szymanski to update i.MX6 APF6/APF6Dev
   device tree with more devices added and adopting DRM bindings for
   display.
 - Random improvements, clean-up and device additions on various boards.

* tag 'imx-dt-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (68 commits)
  ARM: dts: imx6ul-kontron-n6x1x-s: Remove an obsolete comment and fix indentation
  ARM: dts: imx6ul-kontron-n6x1x-s: Add vbus-supply and overcurrent polarity to usb nodes
  ARM: dts: imx6ul-kontron-n6x1x: Add 'chosen' node with 'stdout-path'
  ARM: dts: Add support for two more Kontron evalkit boards 'N6311 S' and 'N6411 S'
  ARM: dts: imx6ul-kontron-n6310-s: Move common nodes to a separate file
  ARM: dts: imx6ul-kontron-n6310-s: Disable the snvs-poweroff driver
  ARM: dts: Add support for two more Kontron SoMs N6311 and N6411
  ARM: dts: imx6ul-kontron-n6310: Move common SoM nodes to a separate file
  ARM: dts: imx7ulp-evk: Use APLL_PFD1 as usdhc's clock source
  ARM: dts: imx: add devicetree for Kobo Clara HD
  ARM: dts: add Netronix E60K02 board common file
  ARM: dts: vf-colibri: fix typo in top-level module compatible
  ARM: dts: imx53-qsb: Use DRM bindings for the Seiko 43WVF1G panel
  ARM: dts: imx53: Spelling s/configration/configuration/
  ARM: dts: imx6ul-14x14-evk: Assign power supplies for magnetometer
  ARM: dts: imx6ul-14x14-evk: Fix the magnetometer node name
  ARM: dts: imx6ul-14x14-evk: Add sensors' GPIO regulator
  ARM: dts: imx6ul: Disable gpt2 by default
  ARM: dts: imx7d: Add missing cooling device properties for CPUs
  ARM: dts: imx6dl: Add missing cooling device properties for CPUs
  ...

Link: https://lore.kernel.org/r/20191105150315.15477-4-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-06 07:47:19 -08:00
commit 405b7b271c
64 changed files with 2622 additions and 1602 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/Makefile
View File

@ -555,7 +555,8 @@ dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk.dtb
imx6sll-evk.dtb \
imx6sll-kobo-clarahd.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-nitrogen6sx.dtb \
imx6sx-sabreauto.dtb \
@ -586,6 +587,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-opos6uldev.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-phytec-segin-lc-rdk-nand.dtb \

306
arch/arm/boot/dts/e60k02.dtsi Normal file
View File

@ -0,0 +1,306 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Andreas Kemnade
* based on works
* Copyright 2016 Freescale Semiconductor, Inc.
* and
* Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd
*
* Netronix E60K02 board common.
* This board is equipped with different SoCs and
* found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and
* the Tolino Shine 3 (with i.MX6SL)
*/
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = &uart1;
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
cover {
label = "Cover";
gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
linux,input-type = <EV_SW>;
wakeup-source;
};
};
leds: leds {
compatible = "gpio-leds";
on {
label = "e60k02:white:on";
gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
};
memory {
reg = <0x80000000 0x20000000>;
};
reg_wifi: regulator-wifi {
compatible = "regulator-fixed";
regulator-name = "SD3_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <20>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
};
};
&i2c1 {
clock-frequency = <100000>;
status = "okay";
lm3630a: backlight@36 {
reg = <0x36>;
compatible = "ti,lm3630a";
enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
led-sources = <0>;
label = "backlight_warm";
default-brightness = <0>;
max-brightness = <255>;
};
led@1 {
reg = <1>;
led-sources = <1>;
label = "backlight_cold";
default-brightness = <0>;
max-brightness = <255>;
};
};
};
&i2c2 {
clock-frequency = <100000>;
status = "okay";
/* TODO: CYTTSP5 touch controller at 0x24 */
/* TODO: TPS65185 PMIC for E Ink at 0x68 */
};
&i2c3 {
clock-frequency = <100000>;
status = "okay";
ricoh619: pmic@32 {
compatible = "ricoh,rc5t619";
reg = <0x32>;
system-power-controller;
regulators {
dcdc1_reg: DCDC1 {
regulator-name = "DCDC1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <900000>;
regulator-suspend-min-microvolt = <900000>;
};
};
/* Core3_3V3 */
dcdc2_reg: DCDC2 {
regulator-name = "DCDC2";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <3300000>;
regulator-suspend-min-microvolt = <3300000>;
};
};
dcdc3_reg: DCDC3 {
regulator-name = "DCDC3";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1140000>;
regulator-suspend-min-microvolt = <1140000>;
};
};
/* Core4_1V2 */
dcdc4_reg: DCDC4 {
regulator-name = "DCDC4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1140000>;
regulator-suspend-min-microvolt = <1140000>;
};
};
/* Core4_1V8 */
dcdc5_reg: DCDC5 {
regulator-name = "DCDC5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1700000>;
regulator-suspend-min-microvolt = <1700000>;
};
};
/* IR_3V3 */
ldo1_reg: LDO1 {
regulator-name = "LDO1";
regulator-boot-on;
};
/* Core1_3V3 */
ldo2_reg: LDO2 {
regulator-name = "LDO2";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <3000000>;
regulator-suspend-min-microvolt = <3000000>;
};
};
/* Core5_1V2 */
ldo3_reg: LDO3 {
regulator-name = "LDO3";
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: LDO4 {
regulator-name = "LDO4";
regulator-boot-on;
};
/* SPD_3V3 */
ldo5_reg: LDO5 {
regulator-name = "LDO5";
regulator-always-on;
regulator-boot-on;
};
/* DDR_0V6 */
ldo6_reg: LDO6 {
regulator-name = "LDO6";
regulator-always-on;
regulator-boot-on;
};
/* VDD_PWM */
ldo7_reg: LDO7 {
regulator-name = "LDO7";
regulator-always-on;
regulator-boot-on;
};
/* ldo_1v8 */
ldo8_reg: LDO8 {
regulator-name = "LDO8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo9_reg: LDO9 {
regulator-name = "LDO9";
regulator-boot-on;
};
ldo10_reg: LDO10 {
regulator-name = "LDO10";
regulator-boot-on;
};
ldortc1_reg: LDORTC1 {
regulator-name = "LDORTC1";
regulator-boot-on;
};
ldortc2_reg: LDORTC2 {
regulator-name = "LDORTC2";
regulator-boot-on;
};
};
};
};
&snvs_rtc {
/* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */
status = "disabled";
};
&uart1 {
status = "okay";
};
&usdhc2 {
non-removable;
status = "okay";
};
&usdhc3 {
vmmc-supply = <&reg_wifi>;
mmc-pwrseq = <&wifi_pwrseq>;
cap-power-off-card;
non-removable;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
disable-over-current;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};

2
arch/arm/boot/dts/imx27.dtsi
View File

@ -585,7 +585,7 @@
status = "disabled";
};
iram: iram@ffff4c00 {
iram: sram@ffff4c00 {
compatible = "mmio-sram";
reg = <0xffff4c00 0xb400>;
};

2
arch/arm/boot/dts/imx31.dtsi
View File

@ -55,7 +55,7 @@
interrupt-parent = <&avic>;
ranges;
iram: iram@1fffc000 {
iram: sram@1fffc000 {
compatible = "mmio-sram";
reg = <0x1fffc000 0x4000>;
#address-cells = <1>;

2
arch/arm/boot/dts/imx51.dtsi
View File

@ -116,7 +116,7 @@
interrupt-parent = <&tzic>;
ranges;
iram: iram@1ffe0000 {
iram: sram@1ffe0000 {
compatible = "mmio-sram";
reg = <0x1ffe0000 0x20000>;
};

44
arch/arm/boot/dts/imx53-qsb-common.dtsi
View File

@ -18,32 +18,26 @@
display0: disp0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
display-timings {
claawvga {
native-mode;
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
port {
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
port@1 {
reg = <1>;
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
@ -84,6 +78,16 @@
};
};
panel {
compatible = "sii,43wvf1g";
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;

2
arch/arm/boot/dts/imx53-usbarmory.dts
View File

@ -120,7 +120,7 @@
};
/*
* UART mode pin header configration
* UART mode pin header configuration
* 3 - GPIO5[26], pull-down 100K
* 4 - GPIO5[27], pull-down 100K
* 5 - TX, pull-up 100K

49
arch/arm/boot/dts/imx6dl-apf6dev.dts
View File

@ -1,49 +1,6 @@
/*
* Copyright 2015 Armadeus Systems
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2015 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6dl.dtsi"

39
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
View File

@ -168,6 +168,21 @@
&i2c3 {
status = "okay";
/*
* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
*/
touchscreen@4a {
compatible = "atmel,maxtouch";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcap_1>;
reg = <0x4a>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
status = "disabled";
};
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
@ -175,6 +190,30 @@
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
&pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
&pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
&pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
>;
pinctrl_pcap_1: pcap1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
>;
};
pinctrl_mxt_ts: mxttsgrp {
fsl,pins = <
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
>;
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};

28
arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
View File

@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
@ -308,7 +309,7 @@
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "disabled";
status = "okay";
oled: oled@3d {
compatible = "solomon,ssd1305fb-i2c";
@ -330,6 +331,18 @@
vcc-supply = <&sw2_reg>;
status = "disabled";
};
touchkeys: keys@5a {
compatible = "fsl,mpr121-touchkey";
reg = <0x5a>;
vdd-supply = <&sw2_reg>;
autorepeat;
linux,keycodes = <KEY_1>, <KEY_2>, <KEY_3>, <KEY_4>, <KEY_5>,
<KEY_6>, <KEY_7>, <KEY_8>, <KEY_9>,
<KEY_BACKSPACE>, <KEY_0>, <KEY_ENTER>;
poll-interval = <50>;
status = "disabled";
};
};
&iomuxc {
@ -447,6 +460,13 @@
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098
MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
@ -532,6 +552,12 @@
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;

8
arch/arm/boot/dts/imx6dl-yapp4-hydra.dts
View File

@ -25,10 +25,6 @@
status = "okay";
};
&i2c3 {
status = "okay";
};
&leds {
status = "okay";
};
@ -45,6 +41,10 @@
status = "okay";
};
&touchkeys {
status = "okay";
};
&usdhc3 {
status = "okay";
};

1
arch/arm/boot/dts/imx6dl.dtsi
View File

@ -64,6 +64,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,

13
arch/arm/boot/dts/imx6q-apalis-eval.dts
View File

@ -167,6 +167,19 @@
&i2c1 {
status = "okay";
/*
* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
*/
touchscreen@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
status = "disabled";
};
pcie-switch@58 {
compatible = "plx,pex8605";
reg = <0x58>;

13
arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
View File

@ -172,6 +172,19 @@
&i2c1 {
status = "okay";
/*
* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
*/
touchscreen@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
status = "disabled";
};
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";

13
arch/arm/boot/dts/imx6q-apalis-ixora.dts
View File

@ -171,6 +171,19 @@
&i2c1 {
status = "okay";
/*
* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
*/
touchscreen@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
status = "disabled";
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;

49
arch/arm/boot/dts/imx6q-apf6dev.dts
View File

@ -1,49 +1,6 @@
/*
* Copyright 2015 Armadeus Systems
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2015 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6q.dtsi"

8
arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
View File

@ -43,6 +43,14 @@
status = "okay";
};
&can1 {
status = "okay";
};
&can2 {
status = "disabled";
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";

2
arch/arm/boot/dts/imx6q-dhcom-som.dtsi
View File

@ -51,13 +51,11 @@
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {

19
arch/arm/boot/dts/imx6q-gw54xx.dts
View File

@ -15,19 +15,16 @@
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_codec>;
simple-audio-card,frame-master = <&sound_codec>;
simple-audio-card,dai-link@0 {
format = "i2s";
sound_cpu: simple-audio-card,cpu {
sound-dai = <&ssi2>;
};
cpu {
sound-dai = <&ssi2>;
};
codec {
bitclock-master;
frame-master;
sound-dai = <&hdmi_receiver>;
};
sound_codec: simple-audio-card,codec {
sound-dai = <&hdmi_receiver>;
};
};
};

3
arch/arm/boot/dts/imx6q.dtsi
View File

@ -73,6 +73,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@ -107,6 +108,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@ -141,6 +143,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,

57
arch/arm/boot/dts/imx6qdl-apalis.dtsi
View File

@ -148,14 +148,16 @@
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_flexcan1_default>;
pinctrl-1 = <&pinctrl_flexcan1_sleep>;
status = "disabled";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_flexcan2_default>;
pinctrl-1 = <&pinctrl_flexcan2_sleep>;
status = "disabled";
};
@ -205,8 +207,11 @@
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -216,8 +221,11 @@
*/
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pfuze100@8 {
@ -372,9 +380,9 @@
*/
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "recovery";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
@ -599,19 +607,32 @@
>;
};
pinctrl_flexcan1: flexcan1grp {
pinctrl_flexcan1_default: flexcan1defgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
pinctrl_flexcan1_sleep: flexcan1slpgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
>;
};
pinctrl_flexcan2_default: flexcan2defgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_flexcan2_sleep: flexcan2slpgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
>;
};
pinctrl_gpio_bl_on: gpioblon {
fsl,pins = <
@ -646,6 +667,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
@ -653,6 +681,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
@ -660,7 +695,7 @@
>;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1

200
arch/arm/boot/dts/imx6qdl-apf6.dtsi
View File

@ -1,66 +1,56 @@
/*
* Copyright 2015 Armadeus Systems
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2015 Armadeus Systems <support@armadeus.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
vin-supply = <&reg_3p3v>;
};
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <15>;
power-off-delay-us = <70>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
};
/* Bluetooth */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
@ -68,6 +58,12 @@
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
mmc-pwrseq = <&usdhc1_pwrseq>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
cap-power-off-card;
keep-power-in-suspend;
non-removable;
status = "okay";
@ -94,65 +90,63 @@
};
&iomuxc {
apf6 {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* WL_EN */
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* WL_IRQ */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
};

422
arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
View File

@ -1,49 +1,6 @@
/*
* Copyright 2015 Armadeus Systems
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2015 Armadeus Systems <support@armadeus.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@ -54,33 +11,35 @@
stdout-path = &uart4;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 191000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <0>;
power-supply = <&reg_5v>;
};
disp0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_disp1>;
pinctrl-0 = <&pinctrl_ipu1_disp0>;
display-timings {
lw700 {
clock-frequency = <33000033>;
hactive = <800>;
vactive = <480>;
hback-porch = <96>;
hfront-porch = <96>;
vback-porch = <20>;
vfront-porch = <21>;
hsync-len = <64>;
vsync-len = <4>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <1>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port {
display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
port@1 {
reg = <1>;
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
@ -111,17 +70,30 @@
};
};
panel {
compatible = "armadeus,st0700-adapt";
power-supply = <&reg_3p3v>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&reg_5v>;
};
reg_usbh1_vbus: regulator-usb-h1-vbus {
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
@ -166,6 +138,7 @@
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
@ -212,6 +185,11 @@
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
};
rtc@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
};
&i2c3 {
@ -261,7 +239,7 @@
};
&usbh1 {
vbus-supply = <&reg_usbh1_vbus>;
vbus-supply = <&reg_5v>;
phy_type = "utmi";
status = "okay";
};
@ -297,178 +275,176 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
apf6dev {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
>;
};
pinctrl_gsm: gsmgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
>;
};
pinctrl_gsm: gsmgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
>;
};
pinctrl_ipu1_disp1: ipu1disp1grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1
>;
};
pinctrl_ipu1_disp0: ipu1disp0grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
>;
};
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
>;
};
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
>;
};
};

35
arch/arm/boot/dts/imx6qdl-colibri.dtsi
View File

@ -166,8 +166,11 @@
*/
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-0 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pfuze100@8 {
@ -312,9 +315,9 @@
*/
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "recovery";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
@ -426,6 +429,9 @@
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh_oc_1>;
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
@ -509,6 +515,13 @@
>;
};
pinctrl_i2c2_gpio: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@ -516,7 +529,7 @@
>;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
@ -615,6 +628,13 @@
>;
};
pinctrl_usbh_oc_1: usbhoc1grp {
fsl,pins = <
/* USBH_OC */
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
@ -681,6 +701,13 @@
>;
};
pinctrl_usbc_id_1: usbc_id-1 {
fsl,pins = <
/* USBC_ID */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071

19
arch/arm/boot/dts/imx6qdl-gw551x.dtsi
View File

@ -105,19 +105,16 @@
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_codec>;
simple-audio-card,frame-master = <&sound_codec>;
simple-audio-card,dai-link@0 {
format = "i2s";
sound_cpu: simple-audio-card,cpu {
sound-dai = <&ssi2>;
};
cpu {
sound-dai = <&ssi2>;
};
codec {
bitclock-master;
frame-master;
sound-dai = <&hdmi_receiver>;
};
sound_codec: simple-audio-card,codec {
sound-dai = <&hdmi_receiver>;
};
};
};

19
arch/arm/boot/dts/imx6qdl-rex.dtsi
View File

@ -132,6 +132,19 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pca9535: gpio-expander@27 {
compatible = "nxp,pca9535";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9535>;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
};
eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
@ -237,6 +250,12 @@
>;
};
pinctrl_pca9535: pca9535grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1

14
arch/arm/boot/dts/imx6qdl-udoo.dtsi
View File

@ -210,6 +210,14 @@
>;
};
pinctrl_usbotg: usbotg {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@ -287,6 +295,12 @@
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;

10
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View File

@ -279,8 +279,18 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
};
};
};
&mipi_csi {

7
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
View File

@ -358,8 +358,10 @@
compatible = "fsl,mma8451";
reg = <0x1c>;
interrupt-parent = <&gpio1>;
interrupt-names = "int1", "int2";
interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT2";
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&reg_3p3v>;
vddio-supply = <&reg_3p3v>;
};
hpa2: amp@60 {
@ -849,7 +851,6 @@
&iomuxc {
pinctrl_accel: accelgrp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x4001b000
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000
>;
};

2
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -525,7 +525,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sl-anatop",
"fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,

324
arch/arm/boot/dts/imx6sll-kobo-clarahd.dts Normal file
View File

@ -0,0 +1,324 @@
// SPDX-License-Identifier: (GPL-2.0)
/*
* Device tree for the Kobo Clara HD ebook reader
*
* Name on mainboard is: 37NB-E60K00+4A4
* Serials start with: E60K02 (a number also seen in
* vendor kernel sources)
*
* This mainboard seems to be equipped with different SoCs.
* In the Kobo Clara HD ebook reader it is an i.MX6SLL
*
* Copyright 2019 Andreas Kemnade
* based on works
* Copyright 2016 Freescale Semiconductor, Inc.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx6sll.dtsi"
#include "e60k02.dtsi"
/ {
model = "Kobo Clara HD";
compatible = "kobo,clarahd", "fsl,imx6sll";
};
&clks {
assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <393216000>;
};
&cpu0 {
arm-supply = <&dcdc3_reg>;
soc-supply = <&dcdc1_reg>;
};
&gpio_keys {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
};
&i2c1 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_sleep>;
};
&i2c2 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_sleep>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */
MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79
MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79
MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79
MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79
MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79
MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79
MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79
MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79
MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79
MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79
MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79
MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79
MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79
MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79
MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79
MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79
MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79
MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79
MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79
MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79
MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79
MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79
MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79
MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79
MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79
MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79
MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79
MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79
MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79
MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x79
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
>;
};
pinctrl_i2c1_sleep: i2c1grp-sleep {
fsl,pins = <
MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
>;
};
pinctrl_i2c2_sleep: i2c2grp-sleep {
fsl,pins = <
MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059
>;
};
pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
fsl,pins = <
MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */
>;
};
pinctrl_ricoh_gpio: ricoh-gpiogrp {
fsl,pins = <
MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
>;
};
pinctrl_usdhc2_sleep: usdhc2grp-sleep {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9
MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9
MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9
MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059
MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059
MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059
MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059
MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059
MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9
MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9
MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
>;
};
pinctrl_usdhc3_sleep: usdhc3grp-sleep {
fsl,pins = <
MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1
MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1
MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1
MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1
>;
};
pinctrl_wifi_power: wifi-powergrp {
fsl,pins = <
MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
>;
};
pinctrl_wifi_reset: wifi-resetgrp {
fsl,pins = <
MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */
>;
};
};
&leds {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
};
&lm3630a {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
};
&reg_wifi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_power>;
};
&ricoh619 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ricoh_gpio>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>;
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>;
};
&wifi_pwrseq {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_reset>;
};

2
arch/arm/boot/dts/imx6sll.dtsi
View File

@ -507,7 +507,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sll-anatop",
"fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x020c8000 0x4000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -594,7 +594,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,

28
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
View File

@ -30,6 +30,16 @@
enable-active-high;
};
reg_sensors: regulator-sensors {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sensors_reg>;
regulator-name = "sensors-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
};
reg_can_3v3: regulator-can-3v3 {
compatible = "regulator-fixed";
regulator-name = "can-3v3";
@ -180,9 +190,11 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
mag3110@e {
magnetometer@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
vdd-supply = <&reg_sensors>;
vddio-supply = <&reg_sensors>;
};
};
@ -266,6 +278,8 @@
&usbotg1 {
dr_mode = "otg";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
status = "okay";
};
@ -448,6 +462,12 @@
>;
};
pinctrl_sensors_reg: sensorsreggrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
@ -499,6 +519,12 @@
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059

148
arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi Normal file
View File

@ -0,0 +1,148 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>
/ {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>; /* will be filled by U-Boot */
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-reset-duration = <1>;
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-handle = <&ethphy1>;
phy-supply = <&reg_3v3>;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
};
/* Bluetooth */
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
uart-has-rtscts;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-1-8-v;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc3_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
/* INT# */
MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
/* RST# */
MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
/* BT_REG_ON */
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
/* WL_REG_ON */
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
/* WL_IRQ */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
>;
};
};

338
arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi Normal file
View File

@ -0,0 +1,338 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>
/ {
chosen {
stdout-path = &uart1;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 191000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_5v>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
user-button {
label = "User button";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
user-led {
label = "User";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
onewire {
compatible = "w1-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_w1>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
};
panel: panel {
compatible = "armadeus,st0700-adapt";
power-supply = <&reg_3v3>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&lcdif_out>;
};
};
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbotg1_vbus: regulator-usbotg1vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg1vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg2_vbus: regulator-usbotg2vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg2vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2_vbus>;
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
vref-supply = <&reg_3v3>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <5000000>;
};
spidev1: spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <5000000>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <400000>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
port {
lcdif_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_pwrkey {
status = "disabled";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xffff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_id>;
vbus-supply = <&reg_usbotg1_vbus>;
dr_mode = "otg";
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usbotg2_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
>;
};
pinctrl_usbotg1_vbus: usbotg1vbusgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
>;
};
};

405
arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
View File

@ -8,413 +8,10 @@
/dts-v1/;
#include "imx6ul-kontron-n6310-som.dtsi"
#include "imx6ul-kontron-n6x1x-s.dtsi"
/ {
model = "Kontron N6310 S";
compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som",
"fsl,imx6ul";
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "debug-led1";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
led2 {
label = "debug-led2";
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "debug-led3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm8 0 5000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref-adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
eeprom@0 {
compatible = "anvo,anv32e61w", "atmel,at25";
reg = <0>;
spi-max-frequency = <20000000>;
spi-cpha;
spi-cpol;
pagesize = <1>;
size = <8192>;
address-width = <16>;
};
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
>;
};
/* FRAM */
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
>;
};
pinctrl_enet2_mdio: enet2mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
/*
* mux unused RTS to make sure it doesn't cause
* any interrupts when it is undefined
*/
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
>;
};
};

95
arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
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@ -6,7 +6,7 @@
*/
#include "imx6ul.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "imx6ul-kontron-n6x1x-som-common.dtsi"
/ {
model = "Kontron N6310 SOM";
@ -18,49 +18,7 @@
};
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
spi-flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
phy-mode = "rmii";
status = "disabled";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
@ -81,54 +39,3 @@
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_out>;
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
>;
};
pinctrl_enet1_mdio: enet1mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
};
pinctrl_reset_out: rstoutgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
};

16
arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6ul-kontron-n6311-som.dtsi"
#include "imx6ul-kontron-n6x1x-s.dtsi"
/ {
model = "Kontron N6311 S";
compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som",
"fsl,imx6ul";
};

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@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ul.dtsi"
#include "imx6ul-kontron-n6x1x-som-common.dtsi"
/ {
model = "Kontron N6311 SOM";
compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul";
memory@80000000 {
reg = <0x80000000 0x20000000>;
device_type = "memory";
};
};
&qspi {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <104000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
partition@8000000 {
label = "ubi2";
reg = <0x08000000 0x18000000>;
};
};
};

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@ -0,0 +1,418 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "debug-led1";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
led2 {
label = "debug-led2";
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "debug-led3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm8 0 5000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref-adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
eeprom@0 {
compatible = "anvo,anv32e61w", "atmel,at25";
reg = <0>;
spi-max-frequency = <20000000>;
spi-cpha;
spi-cpol;
pagesize = <1>;
size = <8192>;
address-width = <16>;
};
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_5v>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
>;
};
pinctrl_enet2_mdio: enet2mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
/*
* mux unused RTS to make sure it doesn't cause
* any interrupts when it is undefined
*/
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
>;
};
};

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@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
stdout-path = &uart4;
};
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
spi-flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
phy-mode = "rmii";
status = "disabled";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_out>;
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
>;
};
pinctrl_enet1_mdio: enet1mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
};
pinctrl_reset_out: rstoutgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
};

195
arch/arm/boot/dts/imx6ul-opos6ul.dtsi
View File

@ -1,193 +1,6 @@
/*
* Copyright 2017 Armadeus Systems <support@armadeus.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2017 Armadeus Systems <support@armadeus.com>
#include "imx6ul.dtsi"
/ {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>; /* will be filled by U-Boot */
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-reset-duration = <1>;
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-handle = <&ethphy1>;
phy-supply = <&reg_3v3>;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
};
/* Bluetooth */
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
uart-has-rtscts;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-1-8-v;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc3_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
/* INT# */
MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
/* RST# */
MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
/* BT_REG_ON */
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
/* WL_REG_ON */
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
/* WL_IRQ */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
>;
};
};
#include "imx6ul-imx6ull-opos6ul.dtsi"

382
arch/arm/boot/dts/imx6ul-opos6uldev.dts
View File

@ -1,293 +1,21 @@
/*
* Copyright 2017 Armadeus Systems <support@armadeus.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2017 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6ul-opos6ul.dtsi"
#include "imx6ul-imx6ull-opos6uldev.dtsi"
/ {
model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
chosen {
stdout-path = &uart1;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 191000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_5v>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
user-button {
label = "User button";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
user-led {
label = "User";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
onewire {
compatible = "w1-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_w1>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
};
panel: panel {
compatible = "armadeus,st0700-adapt";
power-supply = <&reg_3v3>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&lcdif_out>;
};
};
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbotg1_vbus: regulator-usbotg1vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg1vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg2_vbus: regulator-usbotg2vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg2vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2_vbus>;
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
vref-supply = <&reg_3v3>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <5000000>;
};
spidev1: spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <5000000>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock_frequency = <400000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock_frequency = <400000>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
port {
lcdif_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_pwrkey {
status = "disabled";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xffff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_id>;
vbus-supply = <&reg_usbotg1_vbus>;
dr_mode = "otg";
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usbotg2_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board";
compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>;
pinctrl_ecspi4: ecspi4grp {
pinctrl_tamper_gpios: tampergpiosgrp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
@ -299,100 +27,6 @@
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
>;
};
pinctrl_usbotg1_vbus: usbotg1vbusgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
>;
};
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0

2
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
View File

@ -20,7 +20,7 @@
* Set the minimum memory size here and
* let the bootloader set the real size.
*/
memory {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x8000000>;
};

3
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -558,7 +558,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@ -711,6 +711,7 @@
clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
<&clks IMX6UL_CLK_GPT2_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
sdma: sdma@20ec000 {

14
arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
View File

@ -8,6 +8,20 @@
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
power {
label = "Wake-Up";
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
};
/* fixed crystal dedicated to mcp2515 */
clk16m: clk16m {
compatible = "fixed-clock";

2
arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
View File

@ -15,7 +15,7 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
&pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6>;
&pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
};
&iomuxc_snvs {

2
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
View File

@ -26,7 +26,7 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
&pinctrl_gpio4 &pinctrl_gpio5>;
&pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>;
};

64
arch/arm/boot/dts/imx6ull-colibri.dtsi
View File

@ -54,6 +54,18 @@
vref-supply = <&reg_module_3v3_avdd>;
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "disabled";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "disabled";
};
/* Colibri SPI */
&ecspi1 {
cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
@ -62,8 +74,9 @@
};
&fec2 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
@ -198,6 +211,12 @@
assigned-clock-rates = <0>, <198000000>;
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_can_int: canint-grp {
fsl,pins = <
@ -220,6 +239,21 @@
>;
};
pinctrl_enet2_sleep: enet2sleepgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
>;
};
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
@ -234,6 +268,13 @@
>;
};
pinctrl_flexcan1: flexcan1-grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
@ -249,8 +290,6 @@
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
@ -303,6 +342,13 @@
>;
};
pinctrl_gpio7: gpio7-grp { /* CAN1 */
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
>;
};
pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
@ -490,6 +536,12 @@
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
>;
};
pinctrl_wdog: wdog-grp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
};
};
&iomuxc_snvs {
@ -517,19 +569,19 @@
pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
>;
};
pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
>;
};
pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
>;
};

16
arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2019 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6ull-kontron-n6411-som.dtsi"
#include "imx6ul-kontron-n6x1x-s.dtsi"
/ {
model = "Kontron N6411 S";
compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som",
"fsl,imx6ull";
};

40
arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi Normal file
View File

@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ull.dtsi"
#include "imx6ul-kontron-n6x1x-som-common.dtsi"
/ {
model = "Kontron N6411 SOM";
compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull";
memory@80000000 {
reg = <0x80000000 0x20000000>;
device_type = "memory";
};
};
&qspi {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <104000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
partition@8000000 {
label = "ubi2";
reg = <0x08000000 0x18000000>;
};
};
};

6
arch/arm/boot/dts/imx6ull-opos6ul.dtsi Normal file
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>
#include "imx6ull.dtsi"
#include "imx6ul-imx6ull-opos6ul.dtsi"

42
arch/arm/boot/dts/imx6ull-opos6uldev.dts Normal file
View File

@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6ull-opos6ul.dtsi"
#include "imx6ul-imx6ull-opos6uldev.dtsi"
/ {
model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board";
compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull";
};
&iomuxc_snvs {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tamper_gpios>;
pinctrl_tamper_gpios: tampergpiosgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0
>;
};
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
pinctrl_w1: w1grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0
>;
};
};

38
arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
View File

@ -52,6 +52,20 @@
clock-frequency = <16000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
power {
label = "Wake-Up";
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
};
panel: panel {
compatible = "edt,et057090dhu";
backlight = <&bl>;
@ -131,6 +145,21 @@
&i2c4 {
status = "okay";
/*
* Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
*/
touchscreen@4a {
compatible = "atmel,maxtouch";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiotouch>;
reg = <0x4a>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
status = "disabled";
};
/* M41T0M6 real time clock on carrier board */
rtc: m41t0m6@68 {
compatible = "st,m41t0";
@ -186,3 +215,12 @@
vmmc-supply = <&reg_3v3>;
status = "okay";
};
&iomuxc {
pinctrl_gpiotouch: touchgpios {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74
MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14
>;
};
};

30
arch/arm/boot/dts/imx7-colibri.dtsi
View File

@ -322,7 +322,6 @@
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
no-1-8-v;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
disable-wp;
vqmmc-supply = <&reg_LDO2>;
@ -667,6 +666,28 @@
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
@ -737,12 +758,17 @@
pinctrl_gpio_lpsr: gpio1-grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
>;
};
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19
>;
};
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f

6
arch/arm/boot/dts/imx7d.dtsi
View File

@ -22,6 +22,7 @@
reg = <1>;
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_sleep_wait>;
};
};
@ -43,7 +44,8 @@
opp-hz = /bits/ 64 <792000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xf>, <0xf>;
opp-supported-hw = <0xd>, <0xf>;
opp-suspend;
};
opp-996000000 {
@ -51,6 +53,7 @@
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xc>, <0xf>;
opp-suspend;
};
opp-1200000000 {
@ -58,6 +61,7 @@
opp-microvolt = <1225000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0x8>, <0xf>;
opp-suspend;
};
};

2
arch/arm/boot/dts/imx7s.dtsi
View File

@ -559,7 +559,7 @@
anatop: anatop@30360000 {
compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/boot/dts/imx7ulp-evk.dts
View File

@ -77,6 +77,8 @@
};
&usdhc0 {
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;

31
arch/arm/boot/dts/imx7ulp.dtsi
View File

@ -87,13 +87,6 @@
#clock-cells = <0>;
};
mpll: clock-mpll {
compatible = "fixed-clock";
clock-frequency = <480000000>;
clock-output-names = "mpll";
#clock-cells = <0>;
};
ahbbridge0: bus@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -230,8 +223,6 @@
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@ -246,8 +237,6 @@
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@ -258,12 +247,22 @@
compatible = "fsl,imx7ulp-scg1";
reg = <0x403e0000 0x10000>;
clocks = <&rosc>, <&sosc>, <&sirc>,
<&firc>, <&upll>, <&mpll>;
<&firc>, <&upll>;
clock-names = "rosc", "sosc", "sirc",
"firc", "upll", "mpll";
"firc", "upll";
#clock-cells = <1>;
};
wdog1: watchdog@403d0000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x403d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
timeout-sec = <40>;
};
pcc2: clock-controller@403f0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403f0000 0x10000>;
@ -276,13 +275,12 @@
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
"upll", "sosc_bus_clk", "mpll",
"upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
@ -309,13 +307,12 @@
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
"upll", "sosc_bus_clk", "mpll",
"upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
};
};

12
arch/arm/boot/dts/vf-colibri.dtsi
View File

@ -129,8 +129,11 @@
&i2c0 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&nfc {
@ -308,6 +311,13 @@
>;
};
pinctrl_i2c0_gpio: i2c0gpiogrp {
fsl,pins = <
VF610_PAD_PTB14__GPIO_36 0x37ff
VF610_PAD_PTB15__GPIO_37 0x37ff
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
VF610_PAD_PTD23__NF_IO7 0x28df

2
arch/arm/boot/dts/vf500-colibri.dtsi
View File

@ -44,7 +44,7 @@
/ {
model = "Toradex Colibri VF50 COM";
compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
compatible = "toradex,vf500-colibri_vf50", "fsl,vf500";
memory@80000000 {
device_type = "memory";

4
arch/arm/boot/dts/vf610-bk4.dts
View File

@ -259,24 +259,28 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
/delete-property/dma-names;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
/delete-property/dma-names;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
/delete-property/dma-names;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
/delete-property/dma-names;
status = "okay";
};

12
arch/arm/boot/dts/vf610-zii-scu4-aib.dts
View File

@ -183,11 +183,6 @@
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "internal_j9";
};
port@2 {
reg = <2>;
label = "eth_fc_1000_2";
@ -271,11 +266,6 @@
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "internal_j8";
};
port@2 {
reg = <2>;
label = "eth_fc_1000_8";
@ -687,7 +677,6 @@
linux,rs485-enabled-at-boot-time;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
rs485-rts-delay = <0 200>;
status = "okay";
};
@ -695,7 +684,6 @@
linux,rs485-enabled-at-boot-time;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
rs485-rts-delay = <0 200>;
status = "okay";
};