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intel-pinctrl for v5.12-1
* Enable pin control on Intel Alder Lake-P * Traverse through capabilities, convert them to features for the future use The following is an automated git shortlog grouped by driver: intel: - Convert capability list to features - Drop unnecessary check for predefined features - Split intel_pinctrl_add_padgroups() for better maintenance tigerlake: - Add Alder Lake-P ACPI ID -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmAQEgEACgkQb7wzTHR8 rCgJcg/9Hw1Vi6Pe9l+SM7Gt4Cm/aRkYZGdfnDw0e1FgkAfdCmgi/zsBLYNIjiUD cvjKLYf2JSgtA90dprPZWN0SBLdTpY1Yh88TzwGh23Pt8OnDoBP+JcrK07hH/cJ+ u0aUMd+MFNE+Vi3F1s4ENdABJ+uA9kJRpRzA/JGr2UgtII9N7hO+2iq+stfGNiIf lonKkq+MgUfXxLYqRdkoIU/l0G+O86tSlMy1vhdOewyin06kL+FirGQgtoQg/WgD qUXwG3qTZMcwum2q8TDtJioplRR/Vv1o888CdL6KWS25dsZZ13C8k0HNwR04nwFg pzKqrq0Z0IeDNYNP2ThP6/FQ2L1haK4dHjSVdQsbRzI+lQaRL/OAmMBc5Q2HwwbD c7XdJIFfB1ptq+gQF5tpZ0gZKbRNYZuperO/RfJuTPU+Vmtzk8aDi4Zu8GkilcaD JFO5ZX+/6fs/k90TfCNCuoNAEAoKTHjofOh8BXqTtzKT24Sldtchz9YFD7UcvivN H42hMq98XX1ZrcR0xQPLwfC43g4bRwIsZXInQ8z+BNOVpMEQgopxjqZxLGxTPOlA rBjivbEYKdCSp+T3MOz+2tQ160jTg9wAO4Rq/KRT0hxVr+ABGSJGRUcQgNXdvofe Q73iZqiSFTlGPQr0CAFT78tK8cb2mv9b583SeLTgAcZ/wxZP7NA= =9BMa -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v5.12-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.12-1 * Enable pin control on Intel Alder Lake-P * Traverse through capabilities, convert them to features for the future use The following is an automated git shortlog grouped by driver: intel: - Convert capability list to features - Drop unnecessary check for predefined features - Split intel_pinctrl_add_padgroups() for better maintenance tigerlake: - Add Alder Lake-P ACPI ID
This commit is contained in:
Linus Walleij
commit
4007534102
@ -29,6 +29,16 @@
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#define REVID_SHIFT 16
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#define REVID_MASK GENMASK(31, 16)
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#define CAPLIST 0x004
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#define CAPLIST_ID_SHIFT 16
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#define CAPLIST_ID_MASK GENMASK(23, 16)
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#define CAPLIST_ID_GPIO_HW_INFO 1
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#define CAPLIST_ID_PWM 2
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#define CAPLIST_ID_BLINK 3
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#define CAPLIST_ID_EXP 4
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#define CAPLIST_NEXT_SHIFT 0
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#define CAPLIST_NEXT_MASK GENMASK(15, 0)
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#define PADBAR 0x00c
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#define PADOWN_BITS 4
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@ -1321,34 +1331,19 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
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return 0;
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}
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static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
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struct intel_community *community)
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static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
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struct intel_community *community)
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{
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struct intel_padgroup *gpps;
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unsigned int npins = community->npins;
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unsigned int padown_num = 0;
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size_t ngpps, i;
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if (community->gpps)
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ngpps = community->ngpps;
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else
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ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
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size_t i, ngpps = community->ngpps;
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gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
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if (!gpps)
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return -ENOMEM;
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for (i = 0; i < ngpps; i++) {
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if (community->gpps) {
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gpps[i] = community->gpps[i];
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} else {
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unsigned int gpp_size = community->gpp_size;
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gpps[i].reg_num = i;
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gpps[i].base = community->pin_base + i * gpp_size;
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gpps[i].size = min(gpp_size, npins);
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npins -= gpps[i].size;
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}
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gpps[i] = community->gpps[i];
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if (gpps[i].size > 32)
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return -EINVAL;
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@ -1366,6 +1361,38 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
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break;
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}
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gpps[i].padown_num = padown_num;
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padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
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}
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community->gpps = gpps;
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return 0;
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}
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static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
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struct intel_community *community)
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{
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struct intel_padgroup *gpps;
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unsigned int npins = community->npins;
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unsigned int padown_num = 0;
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size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
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if (community->gpp_size > 32)
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return -EINVAL;
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gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
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if (!gpps)
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return -ENOMEM;
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for (i = 0; i < ngpps; i++) {
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unsigned int gpp_size = community->gpp_size;
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gpps[i].reg_num = i;
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gpps[i].base = community->pin_base + i * gpp_size;
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gpps[i].size = min(gpp_size, npins);
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npins -= gpps[i].size;
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gpps[i].padown_num = padown_num;
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/*
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@ -1455,7 +1482,8 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
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for (i = 0; i < pctrl->ncommunities; i++) {
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struct intel_community *community = &pctrl->communities[i];
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void __iomem *regs;
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u32 padbar;
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u32 offset;
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u32 value;
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*community = pctrl->soc->communities[i];
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@ -1463,27 +1491,48 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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/*
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* Determine community features based on the revision if
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* not specified already.
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*/
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if (!community->features) {
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u32 rev;
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rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
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if (rev >= 0x94) {
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community->features |= PINCTRL_FEATURE_DEBOUNCE;
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community->features |= PINCTRL_FEATURE_1K_PD;
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}
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/* Determine community features based on the revision */
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value = readl(regs + REVID);
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if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
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community->features |= PINCTRL_FEATURE_DEBOUNCE;
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community->features |= PINCTRL_FEATURE_1K_PD;
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}
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/* Determine community features based on the capabilities */
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offset = CAPLIST;
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do {
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value = readl(regs + offset);
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switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
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case CAPLIST_ID_GPIO_HW_INFO:
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community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
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break;
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case CAPLIST_ID_PWM:
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community->features |= PINCTRL_FEATURE_PWM;
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break;
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case CAPLIST_ID_BLINK:
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community->features |= PINCTRL_FEATURE_BLINK;
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break;
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case CAPLIST_ID_EXP:
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community->features |= PINCTRL_FEATURE_EXP;
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break;
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default:
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break;
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}
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offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
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} while (offset);
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dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
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/* Read offset of the pad configuration registers */
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padbar = readl(regs + PADBAR);
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offset = readl(regs + PADBAR);
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community->regs = regs;
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community->pad_regs = regs + padbar;
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community->pad_regs = regs + offset;
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ret = intel_pinctrl_add_padgroups(pctrl, community);
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if (community->gpps)
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ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
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else
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ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
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if (ret)
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return ret;
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}
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@ -143,6 +143,10 @@ struct intel_community {
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/* Additional features supported by the hardware */
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#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
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#define PINCTRL_FEATURE_1K_PD BIT(1)
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#define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2)
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#define PINCTRL_FEATURE_PWM BIT(3)
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#define PINCTRL_FEATURE_BLINK BIT(4)
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#define PINCTRL_FEATURE_EXP BIT(5)
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/**
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* PIN_GROUP - Declare a pin group
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@ -748,6 +748,7 @@ static const struct intel_pinctrl_soc_data tglh_soc_data = {
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static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
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{ "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
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{ "INT34C6", (kernel_ulong_t)&tglh_soc_data },
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{ "INTC1055", (kernel_ulong_t)&tgllp_soc_data },
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
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