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MIPS: Alchemy: usb: use clk framework

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Add use of the common clock framework to set and enable the 48MHz
clock source for the onchip OHCI and UDC blocks.

Tested on a DB1500.  (Au1200 and Au1300 use an external 48MHz crystal).

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7467/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss 2014-07-23 16:36:50 +02:00 committed by Ralf Baechle
parent 5a2fb71e73
commit 3feae78416
1 changed files with 40 additions and 7 deletions
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47
arch/mips/alchemy/common/usb.c
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@ -9,6 +9,7 @@
* *
*/ */
#include <linux/clk.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/module.h> #include <linux/module.h>
@ -387,10 +388,25 @@ static inline void au1200_usb_init(void)
udelay(1000); udelay(1000);
} }
static inline void au1000_usb_init(unsigned long rb, int reg) static inline int au1000_usb_init(unsigned long rb, int reg)
{ {
void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
unsigned long r = __raw_readl(base); unsigned long r = __raw_readl(base);
struct clk *c;
/* 48MHz check. Don't init if no one can provide it */
c = clk_get(NULL, "usbh_clk");
if (IS_ERR(c))
return -ENODEV;
if (clk_round_rate(c, 48000000) != 48000000) {
clk_put(c);
return -ENODEV;
}
if (clk_set_rate(c, 48000000)) {
clk_put(c);
return -ENODEV;
}
clk_put(c);
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
r |= USBHEN_BE; r |= USBHEN_BE;
@ -400,6 +416,8 @@ static inline void au1000_usb_init(unsigned long rb, int reg)
__raw_writel(r, base); __raw_writel(r, base);
wmb(); wmb();
udelay(1000); udelay(1000);
return 0;
} }
@ -407,8 +425,15 @@ static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
{ {
void __iomem *base = (void __iomem *)KSEG1ADDR(rb); void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
unsigned long r = __raw_readl(base + creg); unsigned long r = __raw_readl(base + creg);
struct clk *c = clk_get(NULL, "usbh_clk");
if (IS_ERR(c))
return;
if (enable) { if (enable) {
if (clk_prepare_enable(c))
goto out;
__raw_writel(r | USBHEN_CE, base + creg); __raw_writel(r | USBHEN_CE, base + creg);
wmb(); wmb();
udelay(1000); udelay(1000);
@ -423,7 +448,10 @@ static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
} else { } else {
__raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg); __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
wmb(); wmb();
clk_disable_unprepare(c);
} }
out:
clk_put(c);
} }
static inline int au1000_usb_control(int block, int enable, unsigned long rb, static inline int au1000_usb_control(int block, int enable, unsigned long rb,
@ -457,11 +485,11 @@ int alchemy_usb_control(int block, int enable)
case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1500:
case ALCHEMY_CPU_AU1100: case ALCHEMY_CPU_AU1100:
ret = au1000_usb_control(block, enable, ret = au1000_usb_control(block, enable,
AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
break; break;
case ALCHEMY_CPU_AU1550: case ALCHEMY_CPU_AU1550:
ret = au1000_usb_control(block, enable, ret = au1000_usb_control(block, enable,
AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
break; break;
case ALCHEMY_CPU_AU1200: case ALCHEMY_CPU_AU1200:
ret = au1200_usb_control(block, enable); ret = au1200_usb_control(block, enable);
@ -569,14 +597,18 @@ static struct syscore_ops alchemy_usb_pm_ops = {
static int __init alchemy_usb_init(void) static int __init alchemy_usb_init(void)
{ {
int ret = 0;
switch (alchemy_get_cputype()) { switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000: case ALCHEMY_CPU_AU1000:
case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1500:
case ALCHEMY_CPU_AU1100: case ALCHEMY_CPU_AU1100:
au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); ret = au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR,
AU1000_OHCICFG);
break; break;
case ALCHEMY_CPU_AU1550: case ALCHEMY_CPU_AU1550:
au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); ret = au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR,
AU1550_OHCICFG);
break; break;
case ALCHEMY_CPU_AU1200: case ALCHEMY_CPU_AU1200:
au1200_usb_init(); au1200_usb_init();
@ -586,8 +618,9 @@ static int __init alchemy_usb_init(void)
break; break;
} }
register_syscore_ops(&alchemy_usb_pm_ops); if (!ret)
register_syscore_ops(&alchemy_usb_pm_ops);
return 0; return ret;
} }
arch_initcall(alchemy_usb_init); arch_initcall(alchemy_usb_init);