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[PATCH] sata_sis: support SiS966/966L
The SiS966/966L has different PCI-IDs for native mode and AHCI mode. The SiS966 supports four SATA ports only in native mode. Added additional PCI-ID 0x0183 for SiS965/965L. this patch is based on the code from David Wang from SiS Corporation published on SiS Website. Signed-off-by: Uwe Koziolek <uwe.koziolek@gmx.net> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Uwe Koziolek
Jeff Garzik
parent
eaefd5fb7d
commit
3f3e7313e4
@ -42,7 +42,7 @@
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#include <linux/libata.h>
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#define DRV_NAME "sata_sis"
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#define DRV_VERSION "0.6"
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#define DRV_VERSION "0.7"
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enum {
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sis_180 = 0,
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@ -67,9 +67,12 @@ static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static const struct pci_device_id sis_pci_tbl[] = {
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{ PCI_VDEVICE(SI, 0x180), sis_180 },
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{ PCI_VDEVICE(SI, 0x181), sis_180 },
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{ PCI_VDEVICE(SI, 0x182), sis_180 },
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{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
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{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
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{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
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{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
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{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */
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{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */
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{ } /* terminate list */
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};
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@ -142,24 +145,32 @@ MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
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static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, struct pci_dev *pdev)
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{
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unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
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if (port_no) {
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if (device == 0x182)
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addr += SIS182_SATA1_OFS;
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else
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addr += SIS180_SATA1_OFS;
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}
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switch (pdev->device) {
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case 0x0180:
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case 0x0181:
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addr += SIS180_SATA1_OFS;
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break;
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case 0x0182:
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case 0x0183:
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case 0x1182:
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case 0x1183:
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addr += SIS182_SATA1_OFS;
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break;
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}
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}
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return addr;
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}
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static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev);
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u32 val, val2 = 0;
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u8 pmr;
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@ -170,7 +181,8 @@ static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
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pci_read_config_dword(pdev, cfg_addr, &val);
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if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
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if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
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(pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
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pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
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return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */
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@ -179,7 +191,7 @@ static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
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static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev);
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u8 pmr;
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if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
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@ -189,7 +201,8 @@ static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
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pci_write_config_dword(pdev, cfg_addr, val);
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if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
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if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
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(pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
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pci_write_config_dword(pdev, cfg_addr+0x10, val);
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}
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@ -209,7 +222,8 @@ static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
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val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
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if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
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if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
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(pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
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val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
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return (val | val2) & 0xfffffffb;
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@ -229,7 +243,8 @@ static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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sis_scr_cfg_write(ap, sc_reg, val);
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else {
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outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
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if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
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if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
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(pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
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outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
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}
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}
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@ -243,7 +258,7 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
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int pci_dev_busy = 0;
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u8 pmr;
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u8 port2_start;
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u8 port2_start = 0x20;
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if (!printed_version++)
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dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
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@ -282,28 +297,42 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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}
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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if (ent->device != 0x182) {
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switch (ent->device) {
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case 0x0180:
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case 0x0181:
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if ((pmr & SIS_PMR_COMBINED) == 0) {
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dev_printk(KERN_INFO, &pdev->dev,
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"Detected SiS 180/181/964 chipset in SATA mode\n");
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port2_start = 64;
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}
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else {
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} else {
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dev_printk(KERN_INFO, &pdev->dev,
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"Detected SiS 180/181 chipset in combined mode\n");
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port2_start=0;
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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}
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}
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else {
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break;
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case 0x0182:
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case 0x0183:
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pci_read_config_dword ( pdev, 0x6C, &val);
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if (val & (1L << 31)) {
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dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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}
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else
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} else {
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dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
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port2_start = 0x20;
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}
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break;
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case 0x1182:
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case 0x1183:
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pci_read_config_dword(pdev, 0x64, &val);
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if (val & 0x10000000) {
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dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
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} else {
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dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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}
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break;
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}
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probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
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