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staging/rdma/hfi1: Use BIT_ULL macro
Use BIT_ULL macro to fix checkpatch check: CHECK: Prefer using the BIT_ULL macro Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Jubin John <jubin.john@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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@ -93,15 +93,15 @@
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#define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET)
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#define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET)
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/* PBC flags */
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/* PBC flags */
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#define PBC_INTR (1ull << 31)
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#define PBC_INTR BIT_ULL(31)
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#define PBC_DC_INFO_SHIFT (30)
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#define PBC_DC_INFO_SHIFT (30)
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#define PBC_DC_INFO (1ull << PBC_DC_INFO_SHIFT)
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#define PBC_DC_INFO BIT_ULL(PBC_DC_INFO_SHIFT)
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#define PBC_TEST_EBP (1ull << 29)
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#define PBC_TEST_EBP BIT_ULL(29)
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#define PBC_PACKET_BYPASS (1ull << 28)
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#define PBC_PACKET_BYPASS BIT_ULL(28)
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#define PBC_CREDIT_RETURN (1ull << 25)
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#define PBC_CREDIT_RETURN BIT_ULL(25)
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#define PBC_INSERT_BYPASS_ICRC (1ull << 24)
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#define PBC_INSERT_BYPASS_ICRC BIT_ULL(24)
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#define PBC_TEST_BAD_ICRC (1ull << 23)
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#define PBC_TEST_BAD_ICRC BIT_ULL(23)
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#define PBC_FECN (1ull << 22)
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#define PBC_FECN BIT_ULL(22)
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/* PbcInsertHcrc field settings */
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/* PbcInsertHcrc field settings */
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#define PBC_IHCRC_LKDETH 0x0 /* insert @ local KDETH offset */
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#define PBC_IHCRC_LKDETH 0x0 /* insert @ local KDETH offset */
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@ -102,7 +102,7 @@
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#define COUNT_DELAY_SEC(n) ((n) * (1000000 / WAIT_SLEEP_US))
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#define COUNT_DELAY_SEC(n) ((n) * (1000000 / WAIT_SLEEP_US))
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/* GPIO pins */
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/* GPIO pins */
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#define EPROM_WP_N (1ull << 14) /* EPROM write line */
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#define EPROM_WP_N BIT_ULL(14) /* EPROM write line */
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/*
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/*
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* Use the EP mutex to guard against other callers from within the driver.
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* Use the EP mutex to guard against other callers from within the driver.
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@ -107,8 +107,8 @@
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/*
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/*
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* Bits defined in the send DMA descriptor.
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* Bits defined in the send DMA descriptor.
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*/
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*/
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#define SDMA_DESC0_FIRST_DESC_FLAG (1ULL << 63)
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#define SDMA_DESC0_FIRST_DESC_FLAG BIT_ULL(63)
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#define SDMA_DESC0_LAST_DESC_FLAG (1ULL << 62)
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#define SDMA_DESC0_LAST_DESC_FLAG BIT_ULL(62)
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#define SDMA_DESC0_BYTE_COUNT_SHIFT 48
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#define SDMA_DESC0_BYTE_COUNT_SHIFT 48
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#define SDMA_DESC0_BYTE_COUNT_WIDTH 14
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#define SDMA_DESC0_BYTE_COUNT_WIDTH 14
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#define SDMA_DESC0_BYTE_COUNT_MASK \
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#define SDMA_DESC0_BYTE_COUNT_MASK \
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@ -152,8 +152,8 @@
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((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1)
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((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1)
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#define SDMA_DESC1_GENERATION_SMASK \
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#define SDMA_DESC1_GENERATION_SMASK \
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(SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT)
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(SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT)
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#define SDMA_DESC1_INT_REQ_FLAG (1ULL << 1)
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#define SDMA_DESC1_INT_REQ_FLAG BIT_ULL(1)
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#define SDMA_DESC1_HEAD_TO_HOST_FLAG (1ULL << 0)
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#define SDMA_DESC1_HEAD_TO_HOST_FLAG BIT_ULL(0)
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enum sdma_states {
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enum sdma_states {
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sdma_state_s00_hw_down,
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sdma_state_s00_hw_down,
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