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carl9170: import hw/fw header updates
This patch imports all shared header changes from carl9170fw.git. * add some strategic __aligned(4). This allows the compiler generate optimized code for architectures which can't access (unaligned/packed) data efficiently. ("ath9k_hw: optimize all descriptor access functions") * add a forgotten __CARL9170FW__ ifdef around a private firmware-internal struct. * GET_VAL macro helper Very useful for extracting data out of the bit-packed PHY registers. * cosmetic changes e.g.: _CCA_MINCCA_ to just _CCA_MIN_. * version bump 1.8.8.3 -> 1.9.0. Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -97,13 +97,13 @@ struct carl9170_set_key_cmd {
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__le16 type;
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__le16 type;
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u8 macAddr[6];
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u8 macAddr[6];
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u32 key[4];
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u32 key[4];
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} __packed;
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} __packed __aligned(4);
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#define CARL9170_SET_KEY_CMD_SIZE 28
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#define CARL9170_SET_KEY_CMD_SIZE 28
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struct carl9170_disable_key_cmd {
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struct carl9170_disable_key_cmd {
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__le16 user;
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__le16 user;
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__le16 padding;
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__le16 padding;
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} __packed;
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} __packed __aligned(4);
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#define CARL9170_DISABLE_KEY_CMD_SIZE 4
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#define CARL9170_DISABLE_KEY_CMD_SIZE 4
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struct carl9170_u32_list {
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struct carl9170_u32_list {
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@ -206,7 +206,7 @@ struct carl9170_cmd {
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struct carl9170_rx_filter_cmd rx_filter;
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struct carl9170_rx_filter_cmd rx_filter;
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u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
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u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
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} __packed;
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} __packed;
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} __packed;
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} __packed __aligned(4);
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#define CARL9170_TX_STATUS_QUEUE 3
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#define CARL9170_TX_STATUS_QUEUE 3
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#define CARL9170_TX_STATUS_QUEUE_S 0
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#define CARL9170_TX_STATUS_QUEUE_S 0
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@ -216,6 +216,7 @@ struct carl9170_cmd {
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#define CARL9170_TX_STATUS_TRIES (7 << CARL9170_TX_STATUS_TRIES_S)
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#define CARL9170_TX_STATUS_TRIES (7 << CARL9170_TX_STATUS_TRIES_S)
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#define CARL9170_TX_STATUS_SUCCESS 0x80
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#define CARL9170_TX_STATUS_SUCCESS 0x80
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#ifdef __CARL9170FW__
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/*
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/*
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* NOTE:
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* NOTE:
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* Both structs [carl9170_tx_status and _carl9170_tx_status]
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* Both structs [carl9170_tx_status and _carl9170_tx_status]
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@ -232,6 +233,8 @@ struct carl9170_tx_status {
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u8 tries:3;
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u8 tries:3;
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u8 success:1;
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u8 success:1;
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} __packed;
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} __packed;
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#endif /* __CARL9170FW__ */
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struct _carl9170_tx_status {
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struct _carl9170_tx_status {
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/*
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/*
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* This version should be immune to all alignment bugs.
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* This version should be immune to all alignment bugs.
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@ -272,13 +275,15 @@ struct carl9170_rsp {
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struct carl9170_rf_init_result rf_init_res;
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struct carl9170_rf_init_result rf_init_res;
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struct carl9170_u32_list rreg_res;
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struct carl9170_u32_list rreg_res;
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struct carl9170_u32_list echo;
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struct carl9170_u32_list echo;
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#ifdef __CARL9170FW__
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struct carl9170_tx_status tx_status[0];
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struct carl9170_tx_status tx_status[0];
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#endif /* __CARL9170FW__ */
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struct _carl9170_tx_status _tx_status[0];
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struct _carl9170_tx_status _tx_status[0];
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struct carl9170_gpio gpio;
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struct carl9170_gpio gpio;
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struct carl9170_tsf_rsp tsf;
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struct carl9170_tsf_rsp tsf;
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struct carl9170_psm psm;
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struct carl9170_psm psm;
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u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
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u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
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} __packed;
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} __packed;
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} __packed;
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} __packed __aligned(4);
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#endif /* __CARL9170_SHARED_FWCMD_H */
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#endif /* __CARL9170_SHARED_FWCMD_H */
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@ -712,7 +712,8 @@ struct ar9170_stream {
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__le16 tag;
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__le16 tag;
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u8 payload[0];
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u8 payload[0];
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};
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} __packed __aligned(4);
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#define AR9170_STREAM_LEN 4
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#define AR9170_MAX_ACKTABLE_ENTRIES 8
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#define AR9170_MAX_ACKTABLE_ENTRIES 8
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#define AR9170_MAX_VIRTUAL_MAC 7
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#define AR9170_MAX_VIRTUAL_MAC 7
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@ -736,4 +737,8 @@ struct ar9170_stream {
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#define MOD_VAL(reg, value, newvalue) \
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#define MOD_VAL(reg, value, newvalue) \
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(((value) & ~reg) | (((newvalue) << reg##_S) & reg))
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(((value) & ~reg) | (((newvalue) << reg##_S) & reg))
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#define GET_VAL(reg, value) \
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(((value) & reg) >> reg##_S)
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#endif /* __CARL9170_SHARED_HW_H */
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#endif /* __CARL9170_SHARED_HW_H */
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@ -139,8 +139,8 @@
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#define AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
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#define AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
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#define AR9170_PHY_REG_CCA (AR9170_PHY_REG_BASE + 0x0064)
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#define AR9170_PHY_REG_CCA (AR9170_PHY_REG_BASE + 0x0064)
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#define AR9170_PHY_CCA_MINCCA_PWR 0x0ff80000
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#define AR9170_PHY_CCA_MIN_PWR 0x0ff80000
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#define AR9170_PHY_CCA_MINCCA_PWR_S 19
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#define AR9170_PHY_CCA_MIN_PWR_S 19
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#define AR9170_PHY_CCA_THRESH62 0x0007f000
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#define AR9170_PHY_CCA_THRESH62 0x0007f000
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#define AR9170_PHY_CCA_THRESH62_S 12
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#define AR9170_PHY_CCA_THRESH62_S 12
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@ -338,8 +338,8 @@
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#define AR9170_PHY_EXT_CCA_CYCPWR_THR1_S 9
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#define AR9170_PHY_EXT_CCA_CYCPWR_THR1_S 9
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#define AR9170_PHY_EXT_CCA_THRESH62 0x007f0000
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#define AR9170_PHY_EXT_CCA_THRESH62 0x007f0000
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#define AR9170_PHY_EXT_CCA_THRESH62_S 16
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#define AR9170_PHY_EXT_CCA_THRESH62_S 16
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#define AR9170_PHY_EXT_MINCCA_PWR 0xff800000
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#define AR9170_PHY_EXT_CCA_MIN_PWR 0xff800000
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#define AR9170_PHY_EXT_MINCCA_PWR_S 23
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#define AR9170_PHY_EXT_CCA_MIN_PWR_S 23
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#define AR9170_PHY_REG_SFCORR_EXT (AR9170_PHY_REG_BASE + 0x01c0)
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#define AR9170_PHY_REG_SFCORR_EXT (AR9170_PHY_REG_BASE + 0x01c0)
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#define AR9170_PHY_SFCORR_EXT_M1_THRESH 0x0000007f
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#define AR9170_PHY_SFCORR_EXT_M1_THRESH 0x0000007f
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@ -546,19 +546,19 @@
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#define AR9170_PHY_FORCE_XPA_CFG_S 0
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#define AR9170_PHY_FORCE_XPA_CFG_S 0
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#define AR9170_PHY_REG_CH1_CCA (AR9170_PHY_REG_BASE + 0x1064)
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#define AR9170_PHY_REG_CH1_CCA (AR9170_PHY_REG_BASE + 0x1064)
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#define AR9170_PHY_CH1_MINCCA_PWR 0x0ff80000
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#define AR9170_PHY_CH1_CCA_MIN_PWR 0x0ff80000
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#define AR9170_PHY_CH1_MINCCA_PWR_S 19
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#define AR9170_PHY_CH1_CCA_MIN_PWR_S 19
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#define AR9170_PHY_REG_CH2_CCA (AR9170_PHY_REG_BASE + 0x2064)
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#define AR9170_PHY_REG_CH2_CCA (AR9170_PHY_REG_BASE + 0x2064)
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#define AR9170_PHY_CH2_MINCCA_PWR 0x0ff80000
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#define AR9170_PHY_CH2_CCA_MIN_PWR 0x0ff80000
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#define AR9170_PHY_CH2_MINCCA_PWR_S 19
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#define AR9170_PHY_CH2_CCA_MIN_PWR_S 19
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#define AR9170_PHY_REG_CH1_EXT_CCA (AR9170_PHY_REG_BASE + 0x11bc)
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#define AR9170_PHY_REG_CH1_EXT_CCA (AR9170_PHY_REG_BASE + 0x11bc)
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#define AR9170_PHY_CH1_EXT_MINCCA_PWR 0xff800000
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#define AR9170_PHY_CH1_EXT_CCA_MIN_PWR 0xff800000
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#define AR9170_PHY_CH1_EXT_MINCCA_PWR_S 23
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#define AR9170_PHY_CH1_EXT_CCA_MIN_PWR_S 23
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#define AR9170_PHY_REG_CH2_EXT_CCA (AR9170_PHY_REG_BASE + 0x21bc)
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#define AR9170_PHY_REG_CH2_EXT_CCA (AR9170_PHY_REG_BASE + 0x21bc)
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#define AR9170_PHY_CH2_EXT_MINCCA_PWR 0xff800000
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#define AR9170_PHY_CH2_EXT_CCA_MIN_PWR 0xff800000
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#define AR9170_PHY_CH2_EXT_MINCCA_PWR_S 23
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#define AR9170_PHY_CH2_EXT_CCA_MIN_PWR_S 23
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#endif /* __CARL9170_SHARED_PHY_H */
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#endif /* __CARL9170_SHARED_PHY_H */
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@ -1,7 +1,7 @@
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#ifndef __CARL9170_SHARED_VERSION_H
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#ifndef __CARL9170_SHARED_VERSION_H
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#define __CARL9170_SHARED_VERSION_H
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#define __CARL9170_SHARED_VERSION_H
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#define CARL9170FW_VERSION_YEAR 10
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#define CARL9170FW_VERSION_YEAR 10
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#define CARL9170FW_VERSION_MONTH 9
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#define CARL9170FW_VERSION_MONTH 10
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#define CARL9170FW_VERSION_DAY 28
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#define CARL9170FW_VERSION_DAY 29
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#define CARL9170FW_VERSION_GIT "1.8.8.3"
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#define CARL9170FW_VERSION_GIT "1.9.0"
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#endif /* __CARL9170_SHARED_VERSION_H */
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#endif /* __CARL9170_SHARED_VERSION_H */
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