mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
Merge tag 'drm-intel-next-fixes-2016-12-07' of git://anongit.freedesktop.org/git/drm-intel into drm-next
first set of fixes for -next. * tag 'drm-intel-next-fixes-2016-12-07' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: Move priority bumping for flips earlier drm/i915: Hold a reference on the request for its fence chain drm/i915/audio: fix hdmi audio noise issue drm/i915/debugfs: Increment return value of gt.next_seqno drm/i915/debugfs: Drop i915_hws_info drm/i915: Initialize dev_priv->atomic_cdclk_freq at init time drm/i915: Fix cdclk vs. dev_cdclk mess when not recomputing things drm/i915: Make skl_write_{plane,cursor}_wm() static drm/i915: Complete requests in nop_submit_request drm/i915/gvt: fix lock not released bug for dispatch_workload() err path drm/i915/gvt: fix getting 64bit bar size error drm/i915/gvt: fix missing init param.primary
This commit is contained in:
commit
3eff97b2d6
@ -361,6 +361,8 @@ static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
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* leave the bit 3 - bit 0 unchanged.
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*/
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*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
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} else {
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*pval = val;
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}
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}
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@ -177,8 +177,8 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
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rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
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if (IS_ERR(rq)) {
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gvt_err("fail to allocate gem request\n");
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workload->status = PTR_ERR(rq);
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return workload->status;
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ret = PTR_ERR(rq);
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goto out;
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}
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gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
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@ -212,7 +212,8 @@ out:
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if (ret)
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workload->status = ret;
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i915_add_request_no_flush(rq);
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if (!IS_ERR_OR_NULL(rq))
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i915_add_request_no_flush(rq);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return ret;
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}
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@ -460,7 +461,8 @@ complete:
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complete_current_workload(gvt, ring_id);
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i915_gem_request_put(fetch_and_zero(&workload->req));
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if (workload->req)
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i915_gem_request_put(fetch_and_zero(&workload->req));
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if (need_force_wake)
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intel_uncore_forcewake_put(gvt->dev_priv,
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@ -378,6 +378,7 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
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struct intel_vgpu *vgpu;
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param.handle = 0;
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param.primary = 1;
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param.low_gm_sz = type->low_gm_size;
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param.high_gm_sz = type->high_gm_size;
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param.fence_sz = type->fence;
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@ -935,27 +935,6 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
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return 0;
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}
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static int i915_hws_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = m->private;
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struct drm_i915_private *dev_priv = node_to_i915(node);
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struct intel_engine_cs *engine;
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const u32 *hws;
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int i;
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engine = dev_priv->engine[(uintptr_t)node->info_ent->data];
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hws = engine->status_page.page_addr;
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if (hws == NULL)
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return 0;
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for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
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seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i * 4,
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hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
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}
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return 0;
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}
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#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
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static ssize_t
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@ -1047,7 +1026,7 @@ i915_next_seqno_get(void *data, u64 *val)
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{
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struct drm_i915_private *dev_priv = data;
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*val = atomic_read(&dev_priv->gt.global_timeline.next_seqno);
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*val = 1 + atomic_read(&dev_priv->gt.global_timeline.next_seqno);
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return 0;
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}
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@ -5403,10 +5382,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
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{"i915_gem_seqno", i915_gem_seqno_info, 0},
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{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
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{"i915_gem_interrupt", i915_interrupt_info, 0},
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{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
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{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
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{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
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{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
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{"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
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{"i915_guc_info", i915_guc_info, 0},
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{"i915_guc_load_status", i915_guc_load_status_info, 0},
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@ -2764,6 +2764,8 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
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static void nop_submit_request(struct drm_i915_gem_request *request)
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{
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i915_gem_request_submit(request);
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intel_engine_init_global_seqno(request->engine, request->global_seqno);
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}
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static void i915_gem_cleanup_engine(struct intel_engine_cs *engine)
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@ -200,8 +200,8 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
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struct i915_gem_active *active, *next;
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lockdep_assert_held(&request->i915->drm.struct_mutex);
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GEM_BUG_ON(!i915_sw_fence_done(&request->submit));
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GEM_BUG_ON(!i915_sw_fence_done(&request->execute));
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GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
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GEM_BUG_ON(!i915_sw_fence_signaled(&request->execute));
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GEM_BUG_ON(!i915_gem_request_completed(request));
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GEM_BUG_ON(!request->i915->gt.active_requests);
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@ -445,11 +445,17 @@ void i915_gem_request_submit(struct drm_i915_gem_request *request)
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static int __i915_sw_fence_call
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submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
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{
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if (state == FENCE_COMPLETE) {
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struct drm_i915_gem_request *request =
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container_of(fence, typeof(*request), submit);
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struct drm_i915_gem_request *request =
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container_of(fence, typeof(*request), submit);
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switch (state) {
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case FENCE_COMPLETE:
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request->engine->submit_request(request);
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break;
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case FENCE_FREE:
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i915_gem_request_put(request);
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break;
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}
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return NOTIFY_DONE;
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@ -458,6 +464,18 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
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static int __i915_sw_fence_call
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execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
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{
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struct drm_i915_gem_request *request =
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container_of(fence, typeof(*request), execute);
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switch (state) {
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case FENCE_COMPLETE:
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break;
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case FENCE_FREE:
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i915_gem_request_put(request);
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break;
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}
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return NOTIFY_DONE;
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}
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@ -545,8 +563,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
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req->timeline->fence_context,
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__timeline_get_seqno(req->timeline->common));
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i915_sw_fence_init(&req->submit, submit_notify);
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i915_sw_fence_init(&req->execute, execute_notify);
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/* We bump the ref for the fence chain */
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i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify);
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i915_sw_fence_init(&i915_gem_request_get(req)->execute, execute_notify);
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/* Ensure that the execute fence completes after the submit fence -
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* as we complete the execute fence from within the submit fence
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* callback, its completion would otherwise be visible first.
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@ -75,6 +75,11 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
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unsigned long timeout,
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gfp_t gfp);
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static inline bool i915_sw_fence_signaled(const struct i915_sw_fence *fence)
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{
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return atomic_read(&fence->pending) <= 0;
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}
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static inline bool i915_sw_fence_done(const struct i915_sw_fence *fence)
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{
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return atomic_read(&fence->pending) < 0;
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@ -351,10 +351,13 @@ hsw_hdmi_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
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I915_WRITE(HSW_AUD_CFG(pipe), tmp);
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/*
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* Let's disable "Enable CTS or M Prog bit"
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* and let HW calculate the value
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*/
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tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
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tmp &= ~AUD_CONFIG_M_MASK;
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tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
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tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
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tmp |= AUD_M_CTS_M_PROG_ENABLE;
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I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
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}
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@ -12028,7 +12028,6 @@ static void intel_mmio_flip_work_func(struct work_struct *w)
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to_intel_framebuffer(crtc->base.primary->fb);
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struct drm_i915_gem_object *obj = intel_fb->obj;
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i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
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WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
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intel_pipe_update_start(crtc);
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@ -12284,6 +12283,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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i915_add_request_no_flush(request);
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}
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i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
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i915_gem_track_fb(intel_fb_obj(old_fb), obj,
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to_intel_plane(primary)->frontbuffer_bit);
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mutex_unlock(&dev->struct_mutex);
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@ -13995,8 +13995,9 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
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intel_state->cdclk, intel_state->dev_cdclk);
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} else
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} else {
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to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
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}
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intel_modeset_clear_plls(state);
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@ -14097,8 +14098,9 @@ static int intel_atomic_check(struct drm_device *dev,
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if (ret)
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return ret;
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} else
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intel_state->cdclk = dev_priv->cdclk_freq;
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} else {
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intel_state->cdclk = dev_priv->atomic_cdclk_freq;
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}
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ret = drm_atomic_helper_check_planes(dev, state);
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if (ret)
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@ -16485,6 +16487,7 @@ int intel_modeset_init(struct drm_device *dev)
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intel_update_czclk(dev_priv);
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intel_update_cdclk(dev_priv);
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dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
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intel_shared_dpll_init(dev);
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@ -3851,10 +3851,10 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
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I915_WRITE(reg, val);
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}
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void skl_write_plane_wm(struct intel_crtc *intel_crtc,
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const struct skl_plane_wm *wm,
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const struct skl_ddb_allocation *ddb,
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int plane)
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static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
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const struct skl_plane_wm *wm,
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const struct skl_ddb_allocation *ddb,
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int plane)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct drm_device *dev = crtc->dev;
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@ -3875,9 +3875,9 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc,
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&ddb->y_plane[pipe][plane]);
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}
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void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
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const struct skl_plane_wm *wm,
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const struct skl_ddb_allocation *ddb)
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static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
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const struct skl_plane_wm *wm,
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const struct skl_ddb_allocation *ddb)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct drm_device *dev = crtc->dev;
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