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net: davinci_emac: switch to new cpdma layer
This patch hooks up the emac driver with the newly separated cpdma driver. Key differences introduced here: - The old buffer list scheme is no longer required - The original code maintained mac address per rx channel, even if only one rx channel was being used. With this change, mac address is maintained device wide. If support for multiple rx channels is added in future, this will need to be reworked a bit. - The new CPDMA code handles short packets better than before. The earlier code was adjusting the length up, without ensuring that the tail end of the padding was cleared - a possible security issue. This has been fixed to use skb_padto(). Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Michael Williamson <michael.williamson@criticallink.com> Tested-by: Caglar Akyuz <caglarakyuz@gmail.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Cyril Chemparathy
Kevin Hilman
parent
ef8c2dab01
commit
3ef0fdb234
@ -63,6 +63,8 @@
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#include <asm/irq.h>
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#include <asm/page.h>
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#include "davinci_cpdma.h"
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static int debug_level;
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module_param(debug_level, int, 0);
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MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
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@ -113,6 +115,7 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
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#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
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#define EMAC_DEF_TX_CH (0) /* Default 0th channel */
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#define EMAC_DEF_RX_CH (0) /* Default 0th channel */
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#define EMAC_DEF_RX_NUM_DESC (128)
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#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
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#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
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#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
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@ -460,6 +463,9 @@ struct emac_priv {
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u32 hw_ram_addr;
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struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
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struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
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struct cpdma_ctlr *dma;
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struct cpdma_chan *txchan;
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struct cpdma_chan *rxchan;
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u32 link; /* 1=link on, 0=link off */
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u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
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u32 duplex; /* Link duplex: 0=Half, 1=Full */
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@ -624,6 +630,8 @@ static void emac_dump_regs(struct emac_priv *priv)
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emac_read(EMAC_RXMOFOVERRUNS));
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dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
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emac_read(EMAC_RXDMAOVERRUNS));
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cpdma_ctlr_dump(priv->dma);
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}
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/**
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@ -1151,6 +1159,70 @@ static irqreturn_t emac_irq(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
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{
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struct sk_buff *skb = dev_alloc_skb(priv->rx_buf_size);
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if (WARN_ON(!skb))
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return NULL;
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skb->dev = priv->ndev;
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skb_reserve(skb, NET_IP_ALIGN);
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return skb;
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}
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static void emac_rx_handler(void *token, int len, int status)
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{
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struct sk_buff *skb = token;
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struct net_device *ndev = skb->dev;
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struct emac_priv *priv = netdev_priv(ndev);
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struct device *emac_dev = &ndev->dev;
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int ret;
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/* free and bail if we are shutting down */
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if (unlikely(!netif_running(ndev))) {
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dev_kfree_skb_any(skb);
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return;
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}
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/* recycle on recieve error */
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if (status < 0) {
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ndev->stats.rx_errors++;
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goto recycle;
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}
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/* feed received packet up the stack */
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skb_put(skb, len);
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skb->protocol = eth_type_trans(skb, ndev);
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netif_receive_skb(skb);
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ndev->stats.rx_bytes += len;
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ndev->stats.rx_packets++;
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/* alloc a new packet for receive */
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skb = emac_rx_alloc(priv);
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if (!skb) {
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if (netif_msg_rx_err(priv) && net_ratelimit())
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dev_err(emac_dev, "failed rx buffer alloc\n");
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return;
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}
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recycle:
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ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
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skb_tailroom(skb), GFP_KERNEL);
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if (WARN_ON(ret < 0))
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dev_kfree_skb_any(skb);
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}
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static void emac_tx_handler(void *token, int len, int status)
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{
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struct sk_buff *skb = token;
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struct net_device *ndev = skb->dev;
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if (unlikely(netif_queue_stopped(ndev)))
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netif_start_queue(ndev);
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ndev->stats.tx_packets++;
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ndev->stats.tx_bytes += len;
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dev_kfree_skb_any(skb);
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}
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/** EMAC on-chip buffer descriptor memory
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*
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* WARNING: Please note that the on chip memory is used for both TX and RX
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@ -1532,42 +1604,36 @@ static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
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{
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struct device *emac_dev = &ndev->dev;
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int ret_code;
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struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
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struct emac_netpktobj tx_packet; /* packet object */
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struct emac_priv *priv = netdev_priv(ndev);
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/* If no link, return */
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if (unlikely(!priv->link)) {
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if (netif_msg_tx_err(priv) && net_ratelimit())
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dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
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return NETDEV_TX_BUSY;
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goto fail_tx;
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}
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/* Build the buffer and packet objects - Since only single fragment is
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* supported, need not set length and token in both packet & object.
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* Doing so for completeness sake & to show that this needs to be done
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* in multifragment case
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*/
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tx_packet.buf_list = &tx_buf;
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tx_packet.num_bufs = 1; /* only single fragment supported */
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tx_packet.pkt_length = skb->len;
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tx_packet.pkt_token = (void *)skb;
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tx_buf.length = skb->len;
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tx_buf.buf_token = (void *)skb;
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tx_buf.data_ptr = skb->data;
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ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
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ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
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if (unlikely(ret_code < 0)) {
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if (netif_msg_tx_err(priv) && net_ratelimit())
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dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
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goto fail_tx;
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}
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ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
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GFP_KERNEL);
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if (unlikely(ret_code != 0)) {
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if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
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if (netif_msg_tx_err(priv) && net_ratelimit())
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dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
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" err. Out of TX BD's");
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netif_stop_queue(priv->ndev);
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}
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ndev->stats.tx_dropped++;
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return NETDEV_TX_BUSY;
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if (netif_msg_tx_err(priv) && net_ratelimit())
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dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
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goto fail_tx;
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}
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return NETDEV_TX_OK;
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fail_tx:
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ndev->stats.tx_dropped++;
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netif_stop_queue(ndev);
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return NETDEV_TX_BUSY;
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}
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/**
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@ -1588,13 +1654,12 @@ static void emac_dev_tx_timeout(struct net_device *ndev)
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if (netif_msg_tx_err(priv))
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dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
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emac_dump_regs(priv);
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ndev->stats.tx_errors++;
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emac_int_disable(priv);
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emac_stop_txch(priv, EMAC_DEF_TX_CH);
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emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
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emac_init_txch(priv, EMAC_DEF_TX_CH);
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emac_write(EMAC_TXHDP(0), 0);
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emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
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cpdma_chan_stop(priv->txchan);
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cpdma_chan_start(priv->txchan);
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emac_int_enable(priv);
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}
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@ -1915,7 +1980,6 @@ static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
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static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
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{
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struct emac_priv *priv = netdev_priv(ndev);
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struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
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struct device *emac_dev = &priv->ndev->dev;
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struct sockaddr *sa = addr;
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@ -1926,11 +1990,10 @@ static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
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memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
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memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
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/* If the interface is down - rxch is NULL. */
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/* MAC address is configured only after the interface is enabled. */
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if (netif_running(ndev)) {
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memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
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emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
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memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
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emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
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}
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if (netif_msg_drv(priv))
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@ -2139,7 +2202,7 @@ end_emac_rx_bdproc:
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*/
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static int emac_hw_enable(struct emac_priv *priv)
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{
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u32 ch, val, mbp_enable, mac_control;
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u32 val, mbp_enable, mac_control;
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/* Soft reset */
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emac_write(EMAC_SOFTRESET, 1);
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@ -2182,26 +2245,9 @@ static int emac_hw_enable(struct emac_priv *priv)
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emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
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priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
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val = emac_read(EMAC_TXCONTROL);
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val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
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emac_write(EMAC_TXCONTROL, val);
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val = emac_read(EMAC_RXCONTROL);
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val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
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emac_write(EMAC_RXCONTROL, val);
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emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
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for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
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emac_write(EMAC_TXHDP(ch), 0);
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emac_write(EMAC_TXINTMASKSET, BIT(ch));
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}
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for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
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struct emac_rxch *rxch = priv->rxch[ch];
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emac_setmac(priv, ch, rxch->mac_addr);
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emac_write(EMAC_RXINTMASKSET, BIT(ch));
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rxch->queue_active = 1;
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emac_write(EMAC_RXHDP(ch),
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emac_virt_to_phys(rxch->active_queue_head, priv));
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}
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emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
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/* Enable MII */
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val = emac_read(EMAC_MACCONTROL);
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@ -2246,8 +2292,8 @@ static int emac_poll(struct napi_struct *napi, int budget)
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mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
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if (status & mask) {
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num_tx_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
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EMAC_DEF_TX_MAX_SERVICE);
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num_tx_pkts = cpdma_chan_process(priv->txchan,
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EMAC_DEF_TX_MAX_SERVICE);
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} /* TX processing */
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mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
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@ -2256,7 +2302,7 @@ static int emac_poll(struct napi_struct *napi, int budget)
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mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
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if (status & mask) {
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num_rx_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
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num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
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} /* RX processing */
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mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
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@ -2397,9 +2443,9 @@ static int match_first_device(struct device *dev, void *data)
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static int emac_dev_open(struct net_device *ndev)
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{
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struct device *emac_dev = &ndev->dev;
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u32 rc, cnt, ch;
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u32 cnt;
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struct resource *res;
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int q, m;
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int q, m, ret;
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int i = 0;
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int k = 0;
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struct emac_priv *priv = netdev_priv(ndev);
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@ -2411,29 +2457,21 @@ static int emac_dev_open(struct net_device *ndev)
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/* Configuration items */
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priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
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/* Clear basic hardware */
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for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
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emac_write(EMAC_TXHDP(ch), 0);
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emac_write(EMAC_RXHDP(ch), 0);
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emac_write(EMAC_RXHDP(ch), 0);
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emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
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emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
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}
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priv->mac_hash1 = 0;
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priv->mac_hash2 = 0;
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emac_write(EMAC_MACHASH1, 0);
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emac_write(EMAC_MACHASH2, 0);
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/* multi ch not supported - open 1 TX, 1RX ch by default */
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rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
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if (0 != rc) {
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dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
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return rc;
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}
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rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
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if (0 != rc) {
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dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
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return rc;
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for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
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struct sk_buff *skb = emac_rx_alloc(priv);
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if (!skb)
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break;
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ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
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skb_tailroom(skb), GFP_KERNEL);
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if (WARN_ON(ret < 0))
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break;
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}
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/* Request IRQ */
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@ -2458,6 +2496,8 @@ static int emac_dev_open(struct net_device *ndev)
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emac_set_coalesce(ndev, &coal);
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}
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cpdma_ctlr_start(priv->dma);
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priv->phydev = NULL;
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/* use the first phy on the bus if pdata did not give us a phy id */
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if (!priv->phy_id) {
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@ -2545,10 +2585,7 @@ static int emac_dev_stop(struct net_device *ndev)
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netif_carrier_off(ndev);
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emac_int_disable(priv);
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emac_stop_txch(priv, EMAC_DEF_TX_CH);
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emac_stop_rxch(priv, EMAC_DEF_RX_CH);
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emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
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emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
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cpdma_ctlr_stop(priv->dma);
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emac_write(EMAC_SOFTRESET, 1);
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if (priv->phydev)
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@ -2653,9 +2690,10 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
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struct resource *res;
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struct net_device *ndev;
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struct emac_priv *priv;
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unsigned long size;
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unsigned long size, hw_ram_addr;
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struct emac_platform_data *pdata;
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struct device *emac_dev;
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struct cpdma_params dma_params;
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/* obtain emac clock from kernel */
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emac_clk = clk_get(&pdev->dev, NULL);
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@ -2731,11 +2769,40 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
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priv->ctrl_ram_size = pdata->ctrl_ram_size;
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priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
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if (pdata->hw_ram_addr)
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priv->hw_ram_addr = pdata->hw_ram_addr;
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else
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priv->hw_ram_addr = (u32 __force)res->start +
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pdata->ctrl_ram_offset;
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hw_ram_addr = pdata->hw_ram_addr;
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if (!hw_ram_addr)
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hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
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memset(&dma_params, 0, sizeof(dma_params));
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dma_params.dev = emac_dev;
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dma_params.dmaregs = priv->emac_base;
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dma_params.rxthresh = priv->emac_base + 0x120;
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dma_params.rxfree = priv->emac_base + 0x140;
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dma_params.txhdp = priv->emac_base + 0x600;
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dma_params.rxhdp = priv->emac_base + 0x620;
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dma_params.txcp = priv->emac_base + 0x640;
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dma_params.rxcp = priv->emac_base + 0x660;
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dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
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dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
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dma_params.desc_mem_phys = hw_ram_addr;
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dma_params.desc_mem_size = pdata->ctrl_ram_size;
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dma_params.desc_align = 16;
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priv->dma = cpdma_ctlr_create(&dma_params);
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if (!priv->dma) {
|
||||
dev_err(emac_dev, "DaVinci EMAC: Error initializing DMA\n");
|
||||
rc = -ENOMEM;
|
||||
goto no_dma;
|
||||
}
|
||||
|
||||
priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
|
||||
emac_tx_handler);
|
||||
priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
|
||||
emac_rx_handler);
|
||||
if (WARN_ON(!priv->txchan || !priv->rxchan)) {
|
||||
rc = -ENOMEM;
|
||||
goto no_irq_res;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!res) {
|
||||
@ -2778,6 +2845,12 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
|
||||
netdev_reg_err:
|
||||
clk_disable(emac_clk);
|
||||
no_irq_res:
|
||||
if (priv->txchan)
|
||||
cpdma_chan_destroy(priv->txchan);
|
||||
if (priv->rxchan)
|
||||
cpdma_chan_destroy(priv->rxchan);
|
||||
cpdma_ctlr_destroy(priv->dma);
|
||||
no_dma:
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
iounmap(priv->remap_addr);
|
||||
@ -2806,6 +2879,12 @@ static int __devexit davinci_emac_remove(struct platform_device *pdev)
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
if (priv->txchan)
|
||||
cpdma_chan_destroy(priv->txchan);
|
||||
if (priv->rxchan)
|
||||
cpdma_chan_destroy(priv->rxchan);
|
||||
cpdma_ctlr_destroy(priv->dma);
|
||||
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
|
||||
unregister_netdev(ndev);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user