From 3e18a45abc5b20db2e34f02b87226ac2713bbb13 Mon Sep 17 00:00:00 2001 From: Todd Poynor <tpoynor@mvista.com> Date: Fri, 1 Jul 2005 11:27:06 +0100 Subject: [PATCH] [PATCH] ARM: 2782/1: PXA27x MDREFR K0DB4 define Patch from Todd Poynor Add definition of K0DB4 SDCLK<0,3> divide-by-4 control/status bit in the MDREFR register for Intel XScale PXA27x. Signed-off-by: Todd Poynor <tpoynor@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- include/asm-arm/arch-pxa/pxa-regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 803dc92c9038..51f0fe0ac165 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1966,6 +1966,7 @@ #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */