mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 11:44:01 +08:00
dt-bindings: mediatek: audsys: add support for MT8516
Add AUDSYS device tree bindings documentation for MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
a188339ca5
commit
3d8b6e9c77
@ -10,6 +10,7 @@ Required Properties:
|
||||
- "mediatek,mt7622-audsys", "syscon"
|
||||
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt8183-audiosys", "syscon"
|
||||
- "mediatek,mt8516-audsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The AUDSYS controller uses the common clk binding from
|
||||
|
@ -208,4 +208,21 @@
|
||||
#define CLK_TOP_MSDC2_INFRA 176
|
||||
#define CLK_TOP_NR_CLK 177
|
||||
|
||||
/* AUDSYS */
|
||||
|
||||
#define CLK_AUD_AFE 0
|
||||
#define CLK_AUD_I2S 1
|
||||
#define CLK_AUD_22M 2
|
||||
#define CLK_AUD_24M 3
|
||||
#define CLK_AUD_INTDIR 4
|
||||
#define CLK_AUD_APLL2_TUNER 5
|
||||
#define CLK_AUD_APLL_TUNER 6
|
||||
#define CLK_AUD_HDMI 7
|
||||
#define CLK_AUD_SPDF 8
|
||||
#define CLK_AUD_ADC 9
|
||||
#define CLK_AUD_DAC 10
|
||||
#define CLK_AUD_DAC_PREDIS 11
|
||||
#define CLK_AUD_TML 12
|
||||
#define CLK_AUD_NR_CLK 13
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8516_H */
|
||||
|
Loading…
Reference in New Issue
Block a user