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https://github.com/edk2-porting/linux-next.git
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crypto: hisilicon/qm - add callback to support communication
This patch adds 'ping_all_vfs' callback that supports pf send message to all vfs and 'ping_pf' callback that supports vf send message to pf. After receiving the interrupt, the communication destination gets the message by sending mailbox. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Weili Qian
Herbert Xu
parent
e3ac4d20e9
commit
3cd53a27c2
@ -41,6 +41,8 @@
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#define QM_MB_CMD_CQC_BT 0x5
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#define QM_MB_CMD_SQC_VFT_V2 0x6
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#define QM_MB_CMD_STOP_QP 0x8
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#define QM_MB_CMD_SRC 0xc
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#define QM_MB_CMD_DST 0xd
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#define QM_MB_CMD_SEND_BASE 0x300
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#define QM_MB_EVENT_SHIFT 8
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@ -48,6 +50,8 @@
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#define QM_MB_OP_SHIFT 14
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#define QM_MB_CMD_DATA_ADDR_L 0x304
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#define QM_MB_CMD_DATA_ADDR_H 0x308
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#define QM_MB_PING_ALL_VFS 0xffff
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#define QM_MB_CMD_DATA_MASK GENMASK(31, 0)
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/* sqc shift */
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#define QM_SQ_HOP_NUM_SHIFT 0
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@ -180,14 +184,24 @@
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#define QM_MSI_CAP_ENABLE BIT(16)
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/* interfunction communication */
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#define QM_IFC_READY_STATUS 0x100128
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#define QM_IFC_INT_SET_P 0x100130
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#define QM_IFC_INT_CFG 0x100134
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#define QM_IFC_INT_SOURCE_P 0x100138
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#define QM_IFC_INT_SOURCE_V 0x0020
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#define QM_IFC_INT_MASK 0x0024
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#define QM_IFC_INT_STATUS 0x0028
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#define QM_IFC_INT_SET_V 0x002C
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#define QM_IFC_SEND_ALL_VFS GENMASK(6, 0)
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#define QM_IFC_INT_SOURCE_CLR GENMASK(63, 0)
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#define QM_IFC_INT_SOURCE_MASK BIT(0)
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#define QM_IFC_INT_DISABLE BIT(0)
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#define QM_IFC_INT_STATUS_MASK BIT(0)
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#define QM_IFC_INT_SET_MASK BIT(0)
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#define QM_WAIT_DST_ACK 10
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#define QM_MAX_PF_WAIT_COUNT 10
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#define QM_MAX_VF_WAIT_COUNT 40
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#define QM_DFX_MB_CNT_VF 0x104010
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#define QM_DFX_DB_CNT_VF 0x104020
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@ -370,6 +384,8 @@ struct hisi_qm_hw_ops {
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enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
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int (*stop_qp)(struct hisi_qp *qp);
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int (*set_msi)(struct hisi_qm *qm, bool set);
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int (*ping_all_vfs)(struct hisi_qm *qm, u64 cmd);
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int (*ping_pf)(struct hisi_qm *qm, u64 cmd);
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};
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struct qm_dfx_item {
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@ -510,6 +526,18 @@ static bool qm_qp_avail_state(struct hisi_qm *qm, struct hisi_qp *qp,
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return avail;
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}
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static void qm_mb_pre_init(struct qm_mailbox *mailbox, u8 cmd,
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u64 base, u16 queue, bool op)
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{
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mailbox->w0 = cpu_to_le16((cmd) |
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((op) ? 0x1 << QM_MB_OP_SHIFT : 0) |
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(0x1 << QM_MB_BUSY_SHIFT));
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mailbox->queue_num = cpu_to_le16(queue);
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mailbox->base_l = cpu_to_le32(lower_32_bits(base));
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mailbox->base_h = cpu_to_le32(upper_32_bits(base));
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mailbox->rsvd = 0;
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}
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/* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
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static int qm_wait_mb_ready(struct hisi_qm *qm)
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{
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@ -542,44 +570,42 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
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: "memory");
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}
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static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
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{
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if (unlikely(qm_wait_mb_ready(qm))) {
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dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
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goto mb_busy;
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}
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qm_mb_write(qm, mailbox);
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if (unlikely(qm_wait_mb_ready(qm))) {
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dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
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goto mb_busy;
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}
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return 0;
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mb_busy:
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atomic64_inc(&qm->debug.dfx.mb_err_cnt);
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return -EBUSY;
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}
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static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
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bool op)
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{
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struct qm_mailbox mailbox;
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int ret = 0;
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int ret;
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dev_dbg(&qm->pdev->dev, "QM mailbox request to q%u: %u-%llx\n",
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queue, cmd, (unsigned long long)dma_addr);
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mailbox.w0 = cpu_to_le16(cmd |
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(op ? 0x1 << QM_MB_OP_SHIFT : 0) |
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(0x1 << QM_MB_BUSY_SHIFT));
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mailbox.queue_num = cpu_to_le16(queue);
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mailbox.base_l = cpu_to_le32(lower_32_bits(dma_addr));
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mailbox.base_h = cpu_to_le32(upper_32_bits(dma_addr));
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mailbox.rsvd = 0;
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qm_mb_pre_init(&mailbox, cmd, dma_addr, queue, op);
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mutex_lock(&qm->mailbox_lock);
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if (unlikely(qm_wait_mb_ready(qm))) {
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ret = -EBUSY;
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dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
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goto busy_unlock;
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}
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qm_mb_write(qm, &mailbox);
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if (unlikely(qm_wait_mb_ready(qm))) {
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ret = -EBUSY;
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dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
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goto busy_unlock;
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}
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busy_unlock:
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ret = qm_mb_nolock(qm, &mailbox);
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mutex_unlock(&qm->mailbox_lock);
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if (ret)
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atomic64_inc(&qm->debug.dfx.mb_err_cnt);
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return ret;
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}
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@ -1833,6 +1859,25 @@ static int qm_check_dev_error(struct hisi_qm *qm)
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(dev_val & (~qm->err_info.dev_ce_mask));
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}
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static int qm_get_mb_cmd(struct hisi_qm *qm, u64 *msg, u16 fun_num)
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{
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struct qm_mailbox mailbox;
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int ret;
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qm_mb_pre_init(&mailbox, QM_MB_CMD_DST, 0, fun_num, 0);
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mutex_lock(&qm->mailbox_lock);
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ret = qm_mb_nolock(qm, &mailbox);
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if (ret)
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goto err_unlock;
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*msg = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
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((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
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err_unlock:
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mutex_unlock(&qm->mailbox_lock);
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return ret;
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}
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static void qm_clear_cmd_interrupt(struct hisi_qm *qm, u64 vf_mask)
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{
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u32 val;
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@ -1850,6 +1895,108 @@ static int qm_wait_vf_prepare_finish(struct hisi_qm *qm)
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return 0;
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}
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static void qm_trigger_vf_interrupt(struct hisi_qm *qm, u32 fun_num)
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{
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u32 val;
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val = readl(qm->io_base + QM_IFC_INT_CFG);
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val |= ~QM_IFC_SEND_ALL_VFS;
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val |= fun_num;
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writel(val, qm->io_base + QM_IFC_INT_CFG);
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val = readl(qm->io_base + QM_IFC_INT_SET_P);
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val |= QM_IFC_INT_SET_MASK;
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writel(val, qm->io_base + QM_IFC_INT_SET_P);
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}
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static void qm_trigger_pf_interrupt(struct hisi_qm *qm)
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{
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u32 val;
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val = readl(qm->io_base + QM_IFC_INT_SET_V);
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val |= QM_IFC_INT_SET_MASK;
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writel(val, qm->io_base + QM_IFC_INT_SET_V);
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}
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static int qm_ping_all_vfs(struct hisi_qm *qm, u64 cmd)
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{
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struct device *dev = &qm->pdev->dev;
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u32 vfs_num = qm->vfs_num;
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struct qm_mailbox mailbox;
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u64 val = 0;
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int cnt = 0;
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int ret;
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u32 i;
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qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, QM_MB_PING_ALL_VFS, 0);
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mutex_lock(&qm->mailbox_lock);
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/* PF sends command to all VFs by mailbox */
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ret = qm_mb_nolock(qm, &mailbox);
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if (ret) {
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dev_err(dev, "failed to send command to VFs!\n");
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mutex_unlock(&qm->mailbox_lock);
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return ret;
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}
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qm_trigger_vf_interrupt(qm, QM_IFC_SEND_ALL_VFS);
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while (true) {
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msleep(QM_WAIT_DST_ACK);
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val = readq(qm->io_base + QM_IFC_READY_STATUS);
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/* If all VFs acked, PF notifies VFs successfully. */
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if (!(val & GENMASK(vfs_num, 1))) {
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mutex_unlock(&qm->mailbox_lock);
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return 0;
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}
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if (++cnt > QM_MAX_PF_WAIT_COUNT)
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break;
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}
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mutex_unlock(&qm->mailbox_lock);
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/* Check which vf respond timeout. */
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for (i = 1; i <= vfs_num; i++) {
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if (val & BIT(i))
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dev_err(dev, "failed to get response from VF(%u)!\n", i);
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}
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return -ETIMEDOUT;
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}
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static int qm_ping_pf(struct hisi_qm *qm, u64 cmd)
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{
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struct qm_mailbox mailbox;
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int cnt = 0;
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u32 val;
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int ret;
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qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, 0, 0);
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mutex_lock(&qm->mailbox_lock);
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ret = qm_mb_nolock(qm, &mailbox);
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if (ret) {
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dev_err(&qm->pdev->dev, "failed to send command to PF!\n");
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goto unlock;
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}
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qm_trigger_pf_interrupt(qm);
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/* Waiting for PF response */
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while (true) {
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msleep(QM_WAIT_DST_ACK);
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val = readl(qm->io_base + QM_IFC_INT_SET_V);
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if (!(val & QM_IFC_INT_STATUS_MASK))
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break;
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if (++cnt > QM_MAX_VF_WAIT_COUNT) {
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ret = -ETIMEDOUT;
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break;
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}
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}
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unlock:
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mutex_unlock(&qm->mailbox_lock);
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return ret;
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}
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static int qm_stop_qp(struct hisi_qp *qp)
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{
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return qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);
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@ -1968,6 +2115,8 @@ static const struct hisi_qm_hw_ops qm_hw_ops_v3 = {
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.hw_error_handle = qm_hw_error_handle_v2,
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.stop_qp = qm_stop_qp,
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.set_msi = qm_set_msi_v3,
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.ping_all_vfs = qm_ping_all_vfs,
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.ping_pf = qm_ping_pf,
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};
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static void *qm_get_avail_sqe(struct hisi_qp *qp)
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@ -4474,7 +4623,21 @@ static void hisi_qm_controller_reset(struct work_struct *rst_work)
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static void qm_cmd_process(struct work_struct *cmd_process)
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{
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/* handling messages sent by communication source */
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struct hisi_qm *qm = container_of(cmd_process,
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struct hisi_qm, cmd_process);
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struct device *dev = &qm->pdev->dev;
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u64 msg;
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int ret;
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/*
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* Get the msg from source by sending mailbox. Whether message is got
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* successfully, destination needs to ack source by clearing the interrupt.
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*/
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ret = qm_get_mb_cmd(qm, &msg, 0);
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qm_clear_cmd_interrupt(qm, 0);
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if (ret)
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dev_err(dev, "failed to get msg from source!\n");
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}
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/**
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