renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-20 03:04:01 +08:00
Code

ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init

Browse Source 
This patch postpone MPU activation till __after_proc_init (which is
placed in .text section) rather than doing it in __setup_mpu. It
allows us ignore used-only-once .head.text section while programming
PMSAv8 MPU (for PMSAv7 it stays covered anyway).

Tested-by: Szemz? András <sza@esh.hu>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Vladimir Murzin 2018-04-03 10:38:37 +01:00 committed by Russell King
parent 22893aa22b
commit 3c24121039
1 changed files with 22 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
arch/arm/kernel/head-nommu.S
View File

@ -125,11 +125,24 @@ __secondary_data:
*/ */
.text .text
__after_proc_init: __after_proc_init:
#ifdef CONFIG_ARM_MPU
M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
M_CLASS(ldr r3, [r12, 0x50])
AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0
and r3, r3, #(MMFR0_PMSA) @ PMSA field
teq r3, #(MMFR0_PMSAv7) @ PMSA v7
#endif
#ifdef CONFIG_CPU_CP15 #ifdef CONFIG_CPU_CP15
/* /*
* CP15 system control register value returned in r0 from * CP15 system control register value returned in r0 from
* the CPU init function. * the CPU init function.
*/ */
#ifdef CONFIG_ARM_MPU
biceq r0, r0, #CR_BR @ Disable the 'default mem-map'
orreq r0, r0, #CR_M @ Set SCTRL.M (MPU on)
#endif
#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
orr r0, r0, #CR_A orr r0, r0, #CR_A
#else #else
@ -145,7 +158,15 @@ __after_proc_init:
bic r0, r0, #CR_I bic r0, r0, #CR_I
#endif #endif
mcr p15, 0, r0, c1, c0, 0 @ write control reg mcr p15, 0, r0, c1, c0, 0 @ write control reg
isb
#elif defined (CONFIG_CPU_V7M) #elif defined (CONFIG_CPU_V7M)
#ifdef CONFIG_ARM_MPU
ldreq r3, [r12, MPU_CTRL]
biceq r3, #MPU_CTRL_PRIVDEFENA
orreq r3, #MPU_CTRL_ENABLE
streq r3, [r12, MPU_CTRL]
isb
#endif
/* For V7M systems we want to modify the CCR similarly to the SCTLR */ /* For V7M systems we want to modify the CCR similarly to the SCTLR */
#ifdef CONFIG_CPU_DCACHE_DISABLE #ifdef CONFIG_CPU_DCACHE_DISABLE
bic r0, r0, #V7M_SCB_CCR_DC bic r0, r0, #V7M_SCB_CCR_DC
@ -156,9 +177,7 @@ __after_proc_init:
#ifdef CONFIG_CPU_ICACHE_DISABLE #ifdef CONFIG_CPU_ICACHE_DISABLE
bic r0, r0, #V7M_SCB_CCR_IC bic r0, r0, #V7M_SCB_CCR_IC
#endif #endif
movw r3, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR) str r0, [r12, V7M_SCB_CCR]
movt r3, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
str r0, [r3]
#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */ #endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
ret lr ret lr
ENDPROC(__after_proc_init) ENDPROC(__after_proc_init)
@ -282,19 +301,6 @@ M_CLASS(ldr r0, [r12, #MPU_TYPE])
setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
3: isb 3: isb
#endif #endif
/* Enable the MPU */
AR_CLASS(mrc p15, 0, r0, c1, c0, 0) @ Read SCTLR
AR_CLASS(bic r0, r0, #CR_BR) @ Disable the 'default mem-map'
AR_CLASS(orr r0, r0, #CR_M) @ Set SCTRL.M (MPU on)
AR_CLASS(mcr p15, 0, r0, c1, c0, 0) @ Enable MPU
M_CLASS(ldr r0, [r12, #MPU_CTRL])
M_CLASS(bic r0, #MPU_CTRL_PRIVDEFENA)
M_CLASS(orr r0, #MPU_CTRL_ENABLE)
M_CLASS(str r0, [r12, #MPU_CTRL])
isb
ret lr ret lr
ENDPROC(__setup_pmsa_v7) ENDPROC(__setup_pmsa_v7)
@ -352,13 +358,6 @@ ENTRY(__secondary_setup_pmsa_v7)
cmp r4, #0 cmp r4, #0
bgt 1b bgt 1b
/* Enable the MPU */
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
bic r0, r0, #CR_BR @ Disable the 'default mem-map'
orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
isb
ret lr ret lr
ENDPROC(__secondary_setup_pmsa_v7) ENDPROC(__secondary_setup_pmsa_v7)