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staging/rdma/hfi1: Clean up macro indentation
In preparation for implementing Expected TID caching we do some simple clean up of header file macros. Signed-off-by: Mitko Haralanov <mitko.haralanov@intel.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -132,13 +132,14 @@
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* HFI1_CAP_RESERVED_MASK bits.
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*/
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#define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \
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HFI1_CAP_HDRSUPP | \
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HFI1_CAP_MULTI_PKT_EGR | \
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HFI1_CAP_NODROP_RHQ_FULL | \
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HFI1_CAP_NODROP_EGR_FULL | \
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HFI1_CAP_ALLOW_PERM_JKEY | \
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HFI1_CAP_STATIC_RATE_CTRL | \
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HFI1_CAP_PRINT_UNIMPL)
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HFI1_CAP_HDRSUPP | \
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HFI1_CAP_MULTI_PKT_EGR | \
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HFI1_CAP_NODROP_RHQ_FULL | \
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HFI1_CAP_NODROP_EGR_FULL | \
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HFI1_CAP_ALLOW_PERM_JKEY | \
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HFI1_CAP_STATIC_RATE_CTRL | \
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HFI1_CAP_PRINT_UNIMPL | \
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HFI1_CAP_TID_UNMAP)
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/*
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* A set of capability bits that are "global" and are not allowed to be
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* set in the user bitmask.
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@ -127,13 +127,13 @@
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#define HFI1_CMD_TID_UPDATE 4 /* update expected TID entries */
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#define HFI1_CMD_TID_FREE 5 /* free expected TID entries */
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#define HFI1_CMD_CREDIT_UPD 6 /* force an update of PIO credit */
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#define HFI1_CMD_SDMA_STATUS_UPD 7 /* force update of SDMA status ring */
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#define HFI1_CMD_SDMA_STATUS_UPD 7 /* force update of SDMA status ring */
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#define HFI1_CMD_RECV_CTRL 8 /* control receipt of packets */
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#define HFI1_CMD_POLL_TYPE 9 /* set the kind of polling we want */
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#define HFI1_CMD_ACK_EVENT 10 /* ack & clear user status bits */
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#define HFI1_CMD_SET_PKEY 11 /* set context's pkey */
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#define HFI1_CMD_CTXT_RESET 12 /* reset context's HW send context */
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#define HFI1_CMD_SET_PKEY 11 /* set context's pkey */
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#define HFI1_CMD_CTXT_RESET 12 /* reset context's HW send context */
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/* separate EPROM commands from normal PSM commands */
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#define HFI1_CMD_EP_INFO 64 /* read EPROM device ID */
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#define HFI1_CMD_EP_ERASE_CHIP 65 /* erase whole EPROM */
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@ -144,18 +144,18 @@
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#define HFI1_CMD_EP_WRITE_P0 70 /* write EPROM partition 0 */
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#define HFI1_CMD_EP_WRITE_P1 71 /* write EPROM partition 1 */
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#define _HFI1_EVENT_FROZEN_BIT 0
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#define _HFI1_EVENT_LINKDOWN_BIT 1
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#define _HFI1_EVENT_LID_CHANGE_BIT 2
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#define _HFI1_EVENT_LMC_CHANGE_BIT 3
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#define _HFI1_EVENT_SL2VL_CHANGE_BIT 4
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#define _HFI1_EVENT_FROZEN_BIT 0
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#define _HFI1_EVENT_LINKDOWN_BIT 1
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#define _HFI1_EVENT_LID_CHANGE_BIT 2
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#define _HFI1_EVENT_LMC_CHANGE_BIT 3
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#define _HFI1_EVENT_SL2VL_CHANGE_BIT 4
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#define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_SL2VL_CHANGE_BIT
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#define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT)
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#define HFI1_EVENT_LINKDOWN_BIT (1UL << _HFI1_EVENT_LINKDOWN_BIT)
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#define HFI1_EVENT_LID_CHANGE_BIT (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
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#define HFI1_EVENT_LMC_CHANGE_BIT (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
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#define HFI1_EVENT_SL2VL_CHANGE_BIT (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
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#define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT)
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#define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT)
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#define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
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#define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
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#define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
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/*
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* These are the status bits readable (in ASCII form, 64bit value)
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