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SCPI support on ARM64 Juno Development Platform
1. SRAM, MHU mailbox and SCPI support 2. CPU topology using cpu-map 3. Clock support for all the cpus 4. Support for SoC sensors -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJWF7sKAAoJEABBurwxfuKYrEAP/2EqYNykediW8cxct7xyMls3 L6KEOl29HfOJueYT0xY3/9rRuL+a+3rXe/MxnlL/E5FO88080b/ITJFP19DcLW5e /NmV9O4t9S7ZDYiQiGsTjbwaqYXxQA3xcnO25g3oACiMoBety/Axw/FTzEQEpQWL 8UhWbiaONiwlvbe/rOq9VL2gdsN9wpS9W0I+SnCJcHv/UvCRTfalT5wP1azy/liq E+Z8SCinH2Pj0SCVuNg/4YzM0UXDIt2b4fqqp6Yb+lKiUnkACYqK+VsCtT/f+qmY ICMDLDoapq/96SwCCUf0pmvMErx270r8WJeC+Mv4EtkMYnbzGdHIR70yHWCcDbW7 6umapM/QcDfazj2wkPh4dYSTLe1bkijKGEaiMWG5dmn0HtC8dq/mUw1Midgo0z9e n0Mr9dGyMj0oxT0+d1NhuL/XtValCfGxJQu1D3p22KYDliN2Bs8Oa3q0ERArytbe KYhHXJ36AvP66ZjYWTv/Cs3s5RfsW3+ZzDtlB6tl6nh8QgsrUxKcVrCrw15w5qWN 1z00v2Iw5zFe3i5YbPCvGtarYMvGJEyIdv7+D3mIsIU1BA2iff2iB4lq77G7ZoNA UbbeFTZqV8pKtbejDjHkPN4r+Ws5i8A2E3k+kIviqQO46AB8gRyzIUOXj8Di8h0S gMgyo8NkC+6CBlXfPfrC =wBcv -----END PGP SIGNATURE----- Merge tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt Merge "SCPI support on ARM64 Juno Development Platform" from Sudeep Holla: 1. SRAM, MHU mailbox and SCPI support 2. CPU topology using cpu-map 3. Clock support for all the cpus 4. Support for SoC sensors * tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: Add sensor node to Juno dt arm64: dts: add clock support for all the cpus arm64: dts: add CPU topology on Juno arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno
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commit
3b2c05644b
@ -17,6 +17,18 @@
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};
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};
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mailbox: mhu@2b1f0000 {
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compatible = "arm,mhu", "arm,primecell";
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reg = <0x0 0x2b1f0000 0x0 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mhu_lpri_rx",
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"mhu_hpri_rx";
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#mbox-cells = <1>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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reg = <0x0 0x2c010000 0 0x1000>,
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@ -44,6 +56,53 @@
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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};
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sram: sram@2e000000 {
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compatible = "arm,juno-sram-ns", "mmio-sram";
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reg = <0x0 0x2e000000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x2e000000 0x8000>;
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cpu_scp_lpri: scp-shmem@0 {
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compatible = "arm,juno-scp-shmem";
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reg = <0x0 0x200>;
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};
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cpu_scp_hpri: scp-shmem@200 {
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compatible = "arm,juno-scp-shmem";
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reg = <0x200 0x200>;
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};
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};
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scpi {
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compatible = "arm,scpi";
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mboxes = <&mailbox 1>;
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shmem = <&cpu_scp_hpri>;
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clocks {
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compatible = "arm,scpi-clocks";
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scpi_dvfs: scpi_clocks@0 {
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compatible = "arm,scpi-dvfs-clocks";
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#clock-cells = <1>;
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clock-indices = <0>, <1>, <2>;
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clock-output-names = "atlclk", "aplclk","gpuclk";
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};
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scpi_clk: scpi_clocks@3 {
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compatible = "arm,scpi-variable-clocks";
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#clock-cells = <1>;
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clock-indices = <3>, <4>;
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clock-output-names = "pxlclk0", "pxlclk1";
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};
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};
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scpi_sensors0: sensors {
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compatible = "arm,scpi-sensors";
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#thermal-sensor-cells = <1>;
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};
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};
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/include/ "juno-clocks.dtsi"
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dma@7ff00000 {
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@ -34,12 +34,39 @@
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&A57_0>;
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};
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core1 {
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cpu = <&A57_1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&A53_0>;
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};
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core1 {
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cpu = <&A53_1>;
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};
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core2 {
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cpu = <&A53_2>;
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};
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core3 {
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cpu = <&A53_3>;
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};
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};
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};
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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};
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A57_1: cpu@1 {
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@ -48,6 +75,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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};
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A53_0: cpu@100 {
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@ -56,6 +84,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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};
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A53_1: cpu@101 {
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@ -64,6 +93,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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};
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A53_2: cpu@102 {
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@ -72,6 +102,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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};
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A53_3: cpu@103 {
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@ -80,6 +111,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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};
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A57_L2: l2-cache0 {
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@ -34,12 +34,39 @@
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&A57_0>;
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};
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core1 {
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cpu = <&A57_1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&A53_0>;
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};
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core1 {
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cpu = <&A53_1>;
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};
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core2 {
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cpu = <&A53_2>;
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};
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core3 {
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cpu = <&A53_3>;
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};
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};
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};
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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};
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A57_1: cpu@1 {
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@ -48,6 +75,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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};
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A53_0: cpu@100 {
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@ -56,6 +84,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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};
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A53_1: cpu@101 {
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@ -64,6 +93,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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};
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A53_2: cpu@102 {
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@ -72,6 +102,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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};
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A53_3: cpu@103 {
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@ -80,6 +111,7 @@
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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};
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A57_L2: l2-cache0 {
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