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arm64: dts: meson: fix ethernet mac reg format
This fixes the following DT schemas check errors: meson-axg-s400.dt.yaml: soc: ethernet@ff3f0000:reg:0: [0, 4282318848, 0, 65536, 0, 4284695872, 0, 8] is too long meson-axg-s400.dt.yaml: ethernet@ff3f0000: reg: [[0, 4282318848, 0, 65536, 0, 4284695872, 0, 8]] is too short meson-g12a-u200.dt.yaml: soc: ethernet@ff3f0000:reg:0: [0, 4282318848, 0, 65536, 0, 4284695872, 0, 8] is too long meson-g12a-u200.dt.yaml: ethernet@ff3f0000: reg: [[0, 4282318848, 0, 65536, 0, 4284695872, 0, 8]] is too short meson-gxbb-nanopi-k2.dt.yaml: soc: ethernet@c9410000:reg:0: [0, 3376480256, 0, 65536, 0, 3364046144, 0, 4] is too long meson-gxl-s805x-libretech-ac.dt.yaml: soc: ethernet@c9410000:reg:0: [0, 3376480256, 0, 65536, 0, 3364046144, 0, 4] is too lon while here, also drop the redundant reg property from meson-gxl.dtsi because it had the same value as meson-gx.dtsi from which it inherits. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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@ -174,8 +174,8 @@
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compatible = "amlogic,meson-axg-dwmac",
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"snps,dwmac-3.70a",
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"snps,dwmac";
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reg = <0x0 0xff3f0000 0x0 0x10000
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0x0 0xff634540 0x0 0x8>;
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reg = <0x0 0xff3f0000 0x0 0x10000>,
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<0x0 0xff634540 0x0 0x8>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_ETH>,
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@ -98,8 +98,8 @@
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compatible = "amlogic,meson-axg-dwmac",
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"snps,dwmac-3.70a",
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"snps,dwmac";
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reg = <0x0 0xff3f0000 0x0 0x10000
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0x0 0xff634540 0x0 0x8>;
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reg = <0x0 0xff3f0000 0x0 0x10000>,
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<0x0 0xff634540 0x0 0x8>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_ETH>,
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@ -503,8 +503,8 @@
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compatible = "amlogic,meson-gxbb-dwmac",
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"snps,dwmac-3.70a",
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"snps,dwmac";
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reg = <0x0 0xc9410000 0x0 0x10000
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0x0 0xc8834540 0x0 0x4>;
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reg = <0x0 0xc9410000 0x0 0x10000>,
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<0x0 0xc8834540 0x0 0x4>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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rx-fifo-depth = <4096>;
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@ -80,9 +80,6 @@
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};
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ðmac {
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reg = <0x0 0xc9410000 0x0 0x10000
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0x0 0xc8834540 0x0 0x4>;
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_MPLL2>;
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