mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-15 08:44:14 +08:00
Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk-mediatek' into clk-next
- Small non-critical fixes for TI clk driver - Support Mediatek MT8167 clks * clk-simplify: clk: mediatek: fix platform_no_drv_owner.cocci warnings clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init * clk-ti: clk: ti: dra7: add missing clkctrl register for SHA2 instance clk: ti: clockdomain: fix static checker warning clk: ti: autoidle: add checks against NULL pointer reference clk: keystone: sci-clk: add 10% slack to set_rate clk: keystone: sci-clk: cache results of last query rate operation clk: keystone: sci-clk: fix parsing assigned-clock data during probe * clk-tegra: clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate() * clk-rockchip: clk: rockchip: Initialize hw to error to avoid undefined behavior clk: rockchip: rk3399: Support module build clk: rockchip: fix the clk config to support module build clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: rk3308: drop unused mux_timer_src_p * clk-mediatek: clk: mediatek: Add MT8167 clock support dt-bindings: clock: mediatek: add bindings for MT8167 clocks clk: mediatek: add UART0 clock support
This commit is contained in:
Stephen Boyd
commit
3ab9a54f76
@ -15,6 +15,7 @@ Required Properties:
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- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
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- "mediatek,mt7629-apmixedsys"
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- "mediatek,mt8135-apmixedsys"
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- "mediatek,mt8167-apmixedsys", "syscon"
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- "mediatek,mt8173-apmixedsys"
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- "mediatek,mt8183-apmixedsys", "syscon"
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- "mediatek,mt8516-apmixedsys"
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@ -11,6 +11,7 @@ Required Properties:
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- "mediatek,mt6779-audio", "syscon"
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt8167-audiosys", "syscon"
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- "mediatek,mt8183-audiosys", "syscon"
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- "mediatek,mt8516-audsys", "syscon"
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- #clock-cells: Must be 1
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@ -12,6 +12,7 @@ Required Properties:
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- "mediatek,mt6779-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt8167-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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- "mediatek,mt8183-imgsys", "syscon"
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- #clock-cells: Must be 1
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@ -16,6 +16,7 @@ Required Properties:
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- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt7629-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8167-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- "mediatek,mt8183-infracfg", "syscon"
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- "mediatek,mt8516-infracfg", "syscon"
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@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-mfgcfg", "syscon"
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- "mediatek,mt6779-mfgcfg", "syscon"
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- "mediatek,mt8167-mfgcfg", "syscon"
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- "mediatek,mt8183-mfgcfg", "syscon"
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- #clock-cells: Must be 1
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@ -15,6 +15,7 @@ Required Properties:
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- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
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- "mediatek,mt7629-topckgen"
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- "mediatek,mt8135-topckgen"
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- "mediatek,mt8167-topckgen", "syscon"
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- "mediatek,mt8173-topckgen"
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- "mediatek,mt8183-topckgen", "syscon"
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- "mediatek,mt8516-topckgen"
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@ -11,6 +11,7 @@ Required Properties:
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- "mediatek,mt6779-vdecsys", "syscon"
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- "mediatek,mt6797-vdecsys", "syscon"
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- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt8167-vdecsys", "syscon"
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- "mediatek,mt8173-vdecsys", "syscon"
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- "mediatek,mt8183-vdecsys", "syscon"
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- #clock-cells: Must be 1
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@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/rockchip/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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source "drivers/clk/sifive/Kconfig"
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source "drivers/clk/sprd/Kconfig"
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@ -54,6 +54,8 @@ struct sci_clk_provider {
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* @provider: Master clock provider
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* @flags: Flags for the clock
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* @node: Link for handling clocks probed via DT
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* @cached_req: Cached requested freq for determine rate calls
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* @cached_res: Cached result freq for determine rate calls
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*/
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struct sci_clk {
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struct clk_hw hw;
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@ -63,6 +65,8 @@ struct sci_clk {
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struct sci_clk_provider *provider;
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u8 flags;
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struct list_head node;
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unsigned long cached_req;
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unsigned long cached_res;
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};
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#define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw)
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@ -175,6 +179,11 @@ static int sci_clk_determine_rate(struct clk_hw *hw,
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int ret;
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u64 new_rate;
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if (clk->cached_req && clk->cached_req == req->rate) {
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req->rate = clk->cached_res;
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return 0;
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}
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ret = clk->provider->ops->get_best_match_freq(clk->provider->sci,
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clk->dev_id,
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clk->clk_id,
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@ -189,6 +198,9 @@ static int sci_clk_determine_rate(struct clk_hw *hw,
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return ret;
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}
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clk->cached_req = req->rate;
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clk->cached_res = new_rate;
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req->rate = new_rate;
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return 0;
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@ -209,7 +221,8 @@ static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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struct sci_clk *clk = to_sci_clk(hw);
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return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
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clk->clk_id, rate, rate, rate);
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clk->clk_id, rate / 10 * 9, rate,
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rate / 10 * 11);
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}
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/**
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@ -249,6 +262,8 @@ static int sci_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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struct sci_clk *clk = to_sci_clk(hw);
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clk->cached_req = 0;
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return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
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clk->clk_id,
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index + 1 + clk->clk_id);
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@ -522,7 +537,7 @@ static int ti_sci_scan_clocks_from_dt(struct sci_clk_provider *provider)
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np = of_find_node_with_property(np, *clk_name);
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if (!np) {
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clk_name++;
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break;
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continue;
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}
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if (!of_device_is_available(np))
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@ -352,6 +352,54 @@ config COMMON_CLK_MT8135
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help
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This driver supports MediaTek MT8135 clocks.
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config COMMON_CLK_MT8167
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bool "Clock driver for MediaTek MT8167"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8167 basic clocks.
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config COMMON_CLK_MT8167_AUDSYS
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bool "Clock driver for MediaTek MT8167 audsys"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8167 audsys clocks.
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config COMMON_CLK_MT8167_IMGSYS
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bool "Clock driver for MediaTek MT8167 imgsys"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8167 imgsys clocks.
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config COMMON_CLK_MT8167_MFGCFG
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bool "Clock driver for MediaTek MT8167 mfgcfg"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8167 mfgcfg clocks.
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config COMMON_CLK_MT8167_MMSYS
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bool "Clock driver for MediaTek MT8167 mmsys"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8167 mmsys clocks.
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config COMMON_CLK_MT8167_VDECSYS
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bool "Clock driver for MediaTek MT8167 vdecsys"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8167 vdecsys clocks.
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config COMMON_CLK_MT8173
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bool "Clock driver for MediaTek MT8173"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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@ -47,6 +47,12 @@ obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
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obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
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obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
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obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
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obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
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obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
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obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) += clk-mt8167-img.o
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obj-$(CONFIG_COMMON_CLK_MT8167_MFGCFG) += clk-mt8167-mfgcfg.o
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obj-$(CONFIG_COMMON_CLK_MT8167_MMSYS) += clk-mt8167-mm.o
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obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
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obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
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obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
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@ -909,7 +909,6 @@ static struct platform_driver clk_mt6765_drv = {
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.probe = clk_mt6765_probe,
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.driver = {
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.name = "clk-mt6765",
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.owner = THIS_MODULE,
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.of_match_table = of_match_clk_mt6765,
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},
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};
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@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
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"pwm_sel", 19),
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GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
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"pwm_sel", 21),
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GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
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"uart_sel", 22),
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GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
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"uart_sel", 23),
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GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
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@ -582,7 +582,7 @@ CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
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static int mtk_infrasys_init(struct platform_device *pdev)
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{
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int r, i;
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int i;
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struct device_node *node = pdev->dev.of_node;
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if (!infra_clk_data) {
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@ -599,11 +599,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
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mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
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infra_clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
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if (r)
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return r;
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return 0;
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return of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
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}
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#define MT6797_PLL_FMAX (3000UL * MHZ)
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@ -601,7 +601,6 @@ static int mtk_infrasys_init(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
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@ -611,12 +610,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
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mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get,
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clk_data);
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if (r)
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return r;
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return 0;
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return of_clk_add_provider(node, of_clk_src_onecell_get,
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clk_data);
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}
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static int mtk_pericfg_init(struct platform_device *pdev)
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66
drivers/clk/mediatek/clk-mt8167-aud.c
Normal file
66
drivers/clk/mediatek/clk-mt8167-aud.c
Normal file
@ -0,0 +1,66 @@
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// SPDX-License-Identifier: GPL-2.0
|
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/*
|
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* Copyright (c) 2020 MediaTek Inc.
|
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* Copyright (c) 2020 BayLibre, SAS
|
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* Author: James Liao <jamesjj.liao@mediatek.com>
|
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* Fabien Parent <fparent@baylibre.com>
|
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*/
|
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|
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
|
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#include <linux/of_device.h>
|
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#include <linux/platform_device.h>
|
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|
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8167-clk.h>
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|
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static const struct mtk_gate_regs aud_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
|
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|
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#define GATE_AUD(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
|
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.regs = &aud_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
|
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}
|
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|
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static const struct mtk_gate aud_clks[] __initconst = {
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GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
|
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GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
|
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GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
|
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GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
|
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GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
|
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GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
|
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GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
|
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GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
|
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GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
|
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GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
|
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GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
|
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GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
|
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GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
|
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};
|
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|
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static void __init mtk_audsys_init(struct device_node *node)
|
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{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
|
||||
|
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mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
|
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|
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
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if (r)
|
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pr_err("%s(): could not register clock provider: %d\n",
|
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__func__, r);
|
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|
||||
}
|
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CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init);
|
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60
drivers/clk/mediatek/clk-mt8167-img.c
Normal file
60
drivers/clk/mediatek/clk-mt8167-img.c
Normal file
@ -0,0 +1,60 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
* Copyright (c) 2020 BayLibre, SAS
|
||||
* Author: James Liao <jamesjj.liao@mediatek.com>
|
||||
* Fabien Parent <fparent@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt8167-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs img_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
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#define GATE_IMG(_id, _name, _parent, _shift) { \
|
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.id = _id, \
|
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.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &img_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate img_clks[] __initconst = {
|
||||
GATE_IMG(CLK_IMG_LARB1_SMI, "img_larb1_smi", "smi_mm", 0),
|
||||
GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "smi_mm", 5),
|
||||
GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "smi_mm", 6),
|
||||
GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "cam_mm", 7),
|
||||
GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "smi_mm", 8),
|
||||
GATE_IMG(CLK_IMG_VENC, "img_venc", "smi_mm", 9),
|
||||
};
|
||||
|
||||
static void __init mtk_imgsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8167-imgsys", mtk_imgsys_init);
|
||||
58
drivers/clk/mediatek/clk-mt8167-mfgcfg.c
Normal file
58
drivers/clk/mediatek/clk-mt8167-mfgcfg.c
Normal file
@ -0,0 +1,58 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
* Copyright (c) 2020 BayLibre, SAS
|
||||
* Author: James Liao <jamesjj.liao@mediatek.com>
|
||||
* Fabien Parent <fparent@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt8167-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mfg_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_MFG(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mfg_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate mfg_clks[] __initconst = {
|
||||
GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0),
|
||||
GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1),
|
||||
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2),
|
||||
GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3),
|
||||
};
|
||||
|
||||
static void __init mtk_mfgcfg_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init);
|
||||
132
drivers/clk/mediatek/clk-mt8167-mm.c
Normal file
132
drivers/clk/mediatek/clk-mt8167-mm.c
Normal file
@ -0,0 +1,132 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
* Copyright (c) 2020 BayLibre, SAS
|
||||
* Author: James Liao <jamesjj.liao@mediatek.com>
|
||||
* Fabien Parent <fparent@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt8167-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mm0_cg_regs = {
|
||||
.set_ofs = 0x104,
|
||||
.clr_ofs = 0x108,
|
||||
.sta_ofs = 0x100,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs mm1_cg_regs = {
|
||||
.set_ofs = 0x114,
|
||||
.clr_ofs = 0x118,
|
||||
.sta_ofs = 0x110,
|
||||
};
|
||||
|
||||
#define GATE_MM0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_MM1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate mm_clks[] = {
|
||||
/* MM0 */
|
||||
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0),
|
||||
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
|
||||
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2),
|
||||
GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
|
||||
GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6),
|
||||
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7),
|
||||
GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8),
|
||||
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9),
|
||||
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12),
|
||||
GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13),
|
||||
GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14),
|
||||
GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15),
|
||||
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16),
|
||||
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17),
|
||||
GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18),
|
||||
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19),
|
||||
/* MM1 */
|
||||
GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0),
|
||||
GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1),
|
||||
GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2),
|
||||
GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3),
|
||||
GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4),
|
||||
GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5),
|
||||
GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14),
|
||||
GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15),
|
||||
GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16),
|
||||
GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17),
|
||||
GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18),
|
||||
GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19),
|
||||
GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20),
|
||||
GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21),
|
||||
};
|
||||
|
||||
struct clk_mt8167_mm_driver_data {
|
||||
const struct mtk_gate *gates_clk;
|
||||
int gates_num;
|
||||
};
|
||||
|
||||
static const struct clk_mt8167_mm_driver_data mt8167_mmsys_driver_data = {
|
||||
.gates_clk = mm_clks,
|
||||
.gates_num = ARRAY_SIZE(mm_clks),
|
||||
};
|
||||
|
||||
static int clk_mt8167_mm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
const struct clk_mt8167_mm_driver_data *data;
|
||||
struct clk_onecell_data *clk_data;
|
||||
int ret;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
data = &mt8167_mmsys_driver_data;
|
||||
|
||||
ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
|
||||
clk_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt8173_mm_drv = {
|
||||
.driver = {
|
||||
.name = "clk-mt8167-mm",
|
||||
},
|
||||
.probe = clk_mt8167_mm_probe,
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt8173_mm_drv);
|
||||
73
drivers/clk/mediatek/clk-mt8167-vdec.c
Normal file
73
drivers/clk/mediatek/clk-mt8167-vdec.c
Normal file
@ -0,0 +1,73 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
* Copyright (c) 2020 BayLibre, SAS
|
||||
* Author: James Liao <jamesjj.liao@mediatek.com>
|
||||
* Fabien Parent <fparent@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt8167-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs vdec0_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x4,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs vdec1_cg_regs = {
|
||||
.set_ofs = 0x8,
|
||||
.clr_ofs = 0xc,
|
||||
.sta_ofs = 0x8,
|
||||
};
|
||||
|
||||
#define GATE_VDEC0_I(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &vdec0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
#define GATE_VDEC1_I(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &vdec1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate vdec_clks[] __initconst = {
|
||||
/* VDEC0 */
|
||||
GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0),
|
||||
/* VDEC1 */
|
||||
GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0),
|
||||
};
|
||||
|
||||
static void __init mtk_vdecsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8167-vdecsys", mtk_vdecsys_init);
|
||||
1062
drivers/clk/mediatek/clk-mt8167.c
Normal file
1062
drivers/clk/mediatek/clk-mt8167.c
Normal file
File diff suppressed because it is too large
Load Diff
78
drivers/clk/rockchip/Kconfig
Normal file
78
drivers/clk/rockchip/Kconfig
Normal file
@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# common clock support for ROCKCHIP SoC family.
|
||||
|
||||
config COMMON_CLK_ROCKCHIP
|
||||
bool "Rockchip clock controller common support"
|
||||
depends on ARCH_ROCKCHIP
|
||||
default ARCH_ROCKCHIP
|
||||
help
|
||||
Say y here to enable common clock controller for Rockchip platforms.
|
||||
|
||||
if COMMON_CLK_ROCKCHIP
|
||||
config CLK_PX30
|
||||
bool "Rockchip PX30 clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for PX30 Clock Driver.
|
||||
|
||||
config CLK_RV110X
|
||||
bool "Rockchip RV110x clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RV110x Clock Driver.
|
||||
|
||||
config CLK_RK3036
|
||||
bool "Rockchip RK3036 clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3036 Clock Driver.
|
||||
|
||||
config CLK_RK312X
|
||||
bool "Rockchip RK312x clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RK312x Clock Driver.
|
||||
|
||||
config CLK_RK3188
|
||||
bool "Rockchip RK3188 clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3188 Clock Driver.
|
||||
|
||||
config CLK_RK322X
|
||||
bool "Rockchip RK322x clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RK322x Clock Driver.
|
||||
|
||||
config CLK_RK3288
|
||||
bool "Rockchip RK3288 clock controller support"
|
||||
depends on ARM
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3288 Clock Driver.
|
||||
|
||||
config CLK_RK3308
|
||||
bool "Rockchip RK3308 clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3308 Clock Driver.
|
||||
|
||||
config CLK_RK3328
|
||||
bool "Rockchip RK3328 clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3328 Clock Driver.
|
||||
|
||||
config CLK_RK3368
|
||||
bool "Rockchip RK3368 clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3368 Clock Driver.
|
||||
|
||||
config CLK_RK3399
|
||||
tristate "Rockchip RK3399 clock controller support"
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3399 Clock Driver.
|
||||
endif
|
||||
@ -3,24 +3,26 @@
|
||||
# Rockchip Clock specific Makefile
|
||||
#
|
||||
|
||||
obj-y += clk.o
|
||||
obj-y += clk-pll.o
|
||||
obj-y += clk-cpu.o
|
||||
obj-y += clk-half-divider.o
|
||||
obj-y += clk-inverter.o
|
||||
obj-y += clk-mmc-phase.o
|
||||
obj-y += clk-muxgrf.o
|
||||
obj-y += clk-ddr.o
|
||||
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
|
||||
obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
|
||||
|
||||
obj-y += clk-px30.o
|
||||
obj-y += clk-rv1108.o
|
||||
obj-y += clk-rk3036.o
|
||||
obj-y += clk-rk3128.o
|
||||
obj-y += clk-rk3188.o
|
||||
obj-y += clk-rk3228.o
|
||||
obj-y += clk-rk3288.o
|
||||
obj-y += clk-rk3308.o
|
||||
obj-y += clk-rk3328.o
|
||||
obj-y += clk-rk3368.o
|
||||
obj-y += clk-rk3399.o
|
||||
clk-rockchip-y += clk.o
|
||||
clk-rockchip-y += clk-pll.o
|
||||
clk-rockchip-y += clk-cpu.o
|
||||
clk-rockchip-y += clk-half-divider.o
|
||||
clk-rockchip-y += clk-inverter.o
|
||||
clk-rockchip-y += clk-mmc-phase.o
|
||||
clk-rockchip-y += clk-muxgrf.o
|
||||
clk-rockchip-y += clk-ddr.o
|
||||
clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
|
||||
|
||||
obj-$(CONFIG_CLK_PX30) += clk-px30.o
|
||||
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
|
||||
obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
|
||||
obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
|
||||
obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
|
||||
obj-$(CONFIG_CLK_RK322X) += clk-rk3228.o
|
||||
obj-$(CONFIG_CLK_RK3288) += clk-rk3288.o
|
||||
obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
|
||||
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
|
||||
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
|
||||
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
|
||||
|
||||
@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
|
||||
return clk;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);
|
||||
|
||||
@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
|
||||
unsigned long flags,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_hw *hw = ERR_PTR(-ENOMEM);
|
||||
struct clk_mux *mux = NULL;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_divider *div = NULL;
|
||||
@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
|
||||
div_ops = &clk_half_divider_ops;
|
||||
}
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
mux ? &mux->hw : NULL, mux_ops,
|
||||
div ? &div->hw : NULL, div_ops,
|
||||
gate ? &gate->hw : NULL, gate_ops,
|
||||
flags);
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
mux ? &mux->hw : NULL, mux_ops,
|
||||
div ? &div->hw : NULL, div_ops,
|
||||
gate ? &gate->hw : NULL, gate_ops,
|
||||
flags);
|
||||
if (IS_ERR(hw))
|
||||
goto err_div;
|
||||
|
||||
return clk;
|
||||
return hw->clk;
|
||||
err_div:
|
||||
kfree(gate);
|
||||
err_gate:
|
||||
kfree(mux);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
return ERR_CAST(hw);
|
||||
}
|
||||
|
||||
@ -133,7 +133,6 @@ PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
|
||||
PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
|
||||
PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
|
||||
PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
|
||||
PNAME(mux_timer_src_p) = { "xin24m", "clk_rtc32k" };
|
||||
PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
|
||||
PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
|
||||
PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
|
||||
|
||||
@ -5,9 +5,11 @@
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <dt-bindings/clock/rk3399-cru.h>
|
||||
@ -1600,3 +1602,57 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
|
||||
rockchip_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
|
||||
|
||||
struct clk_rk3399_inits {
|
||||
void (*inits)(struct device_node *np);
|
||||
};
|
||||
|
||||
static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
|
||||
.inits = rk3399_pmu_clk_init,
|
||||
};
|
||||
|
||||
static const struct clk_rk3399_inits clk_rk3399_cru_init = {
|
||||
.inits = rk3399_clk_init,
|
||||
};
|
||||
|
||||
static const struct of_device_id clk_rk3399_match_table[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3399-cru",
|
||||
.data = &clk_rk3399_cru_init,
|
||||
}, {
|
||||
.compatible = "rockchip,rk3399-pmucru",
|
||||
.data = &clk_rk3399_pmucru_init,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
|
||||
|
||||
static int __init clk_rk3399_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *match;
|
||||
const struct clk_rk3399_inits *init_data;
|
||||
|
||||
match = of_match_device(clk_rk3399_match_table, &pdev->dev);
|
||||
if (!match || !match->data)
|
||||
return -EINVAL;
|
||||
|
||||
init_data = match->data;
|
||||
if (init_data->inits)
|
||||
init_data->inits(np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_rk3399_driver = {
|
||||
.driver = {
|
||||
.name = "clk-rk3399",
|
||||
.of_match_table = clk_rk3399_match_table,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
|
||||
|
||||
MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:clk-rk3399");
|
||||
|
||||
@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
|
||||
u8 gate_shift, u8 gate_flags, unsigned long flags,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_hw *hw;
|
||||
struct clk_mux *mux = NULL;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_divider *div = NULL;
|
||||
@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const char *name,
|
||||
: &clk_divider_ops;
|
||||
}
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
mux ? &mux->hw : NULL, mux_ops,
|
||||
div ? &div->hw : NULL, div_ops,
|
||||
gate ? &gate->hw : NULL, gate_ops,
|
||||
flags);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
goto err_composite;
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
mux ? &mux->hw : NULL, mux_ops,
|
||||
div ? &div->hw : NULL, div_ops,
|
||||
gate ? &gate->hw : NULL, gate_ops,
|
||||
flags);
|
||||
if (IS_ERR(hw)) {
|
||||
kfree(div);
|
||||
kfree(gate);
|
||||
return ERR_CAST(hw);
|
||||
}
|
||||
|
||||
return clk;
|
||||
err_composite:
|
||||
kfree(div);
|
||||
return hw->clk;
|
||||
err_div:
|
||||
kfree(gate);
|
||||
err_gate:
|
||||
@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch(
|
||||
unsigned long flags, struct rockchip_clk_branch *child,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct rockchip_clk_frac *frac;
|
||||
struct clk *clk;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_fractional_divider *div = NULL;
|
||||
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
|
||||
@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch(
|
||||
div->approximation = rockchip_fractional_approximation;
|
||||
div_ops = &clk_fractional_divider_ops;
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
NULL, NULL,
|
||||
&div->hw, div_ops,
|
||||
gate ? &gate->hw : NULL, gate_ops,
|
||||
flags | CLK_SET_RATE_UNGATE);
|
||||
if (IS_ERR(clk)) {
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
NULL, NULL,
|
||||
&div->hw, div_ops,
|
||||
gate ? &gate->hw : NULL, gate_ops,
|
||||
flags | CLK_SET_RATE_UNGATE);
|
||||
if (IS_ERR(hw)) {
|
||||
kfree(frac);
|
||||
return clk;
|
||||
return ERR_CAST(hw);
|
||||
}
|
||||
|
||||
if (child) {
|
||||
@ -292,7 +290,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
||||
mux_clk = clk_register(NULL, &frac_mux->hw);
|
||||
if (IS_ERR(mux_clk)) {
|
||||
kfree(frac);
|
||||
return clk;
|
||||
return mux_clk;
|
||||
}
|
||||
|
||||
rockchip_clk_add_lookup(ctx, mux_clk, child->id);
|
||||
@ -301,7 +299,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
||||
if (frac->mux_frac_idx >= 0) {
|
||||
pr_debug("%s: found fractional parent in mux at pos %d\n",
|
||||
__func__, frac->mux_frac_idx);
|
||||
ret = clk_notifier_register(clk, &frac->clk_nb);
|
||||
ret = clk_notifier_register(hw->clk, &frac->clk_nb);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register clock notifier for %s\n",
|
||||
__func__, name);
|
||||
@ -311,7 +309,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
||||
}
|
||||
}
|
||||
|
||||
return clk;
|
||||
return hw->clk;
|
||||
}
|
||||
|
||||
static struct clk *rockchip_clk_register_factor_branch(const char *name,
|
||||
@ -320,7 +318,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
|
||||
int gate_offset, u8 gate_shift, u8 gate_flags,
|
||||
unsigned long flags, spinlock_t *lock)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_hw *hw;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_fixed_factor *fix = NULL;
|
||||
|
||||
@ -349,20 +347,22 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
|
||||
fix->mult = mult;
|
||||
fix->div = div;
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
NULL, NULL,
|
||||
&fix->hw, &clk_fixed_factor_ops,
|
||||
&gate->hw, &clk_gate_ops, flags);
|
||||
if (IS_ERR(clk)) {
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
NULL, NULL,
|
||||
&fix->hw, &clk_fixed_factor_ops,
|
||||
&gate->hw, &clk_gate_ops, flags);
|
||||
if (IS_ERR(hw)) {
|
||||
kfree(fix);
|
||||
kfree(gate);
|
||||
return ERR_CAST(hw);
|
||||
}
|
||||
|
||||
return clk;
|
||||
return hw->clk;
|
||||
}
|
||||
|
||||
struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
|
||||
void __iomem *base, unsigned long nr_clks)
|
||||
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
|
||||
void __iomem *base,
|
||||
unsigned long nr_clks)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
struct clk **clk_table;
|
||||
@ -394,14 +394,16 @@ err_free:
|
||||
kfree(ctx);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_init);
|
||||
|
||||
void __init rockchip_clk_of_add_provider(struct device_node *np,
|
||||
struct rockchip_clk_provider *ctx)
|
||||
void rockchip_clk_of_add_provider(struct device_node *np,
|
||||
struct rockchip_clk_provider *ctx)
|
||||
{
|
||||
if (of_clk_add_provider(np, of_clk_src_onecell_get,
|
||||
&ctx->clk_data))
|
||||
pr_err("%s: could not register clk provider\n", __func__);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
|
||||
|
||||
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
||||
struct clk *clk, unsigned int id)
|
||||
@ -409,8 +411,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
||||
if (ctx->clk_data.clks && id)
|
||||
ctx->clk_data.clks[id] = clk;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup);
|
||||
|
||||
void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
||||
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_pll_clock *list,
|
||||
unsigned int nr_pll, int grf_lock_offset)
|
||||
{
|
||||
@ -433,11 +436,11 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
||||
rockchip_clk_add_lookup(ctx, clk, list->id);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
|
||||
|
||||
void __init rockchip_clk_register_branches(
|
||||
struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk)
|
||||
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk = NULL;
|
||||
unsigned int idx;
|
||||
@ -566,14 +569,15 @@ void __init rockchip_clk_register_branches(
|
||||
rockchip_clk_add_lookup(ctx, clk, list->id);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
|
||||
|
||||
void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
||||
unsigned int lookup_id,
|
||||
const char *name, const char *const *parent_names,
|
||||
u8 num_parents,
|
||||
const struct rockchip_cpuclk_reg_data *reg_data,
|
||||
const struct rockchip_cpuclk_rate_table *rates,
|
||||
int nrates)
|
||||
void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
||||
unsigned int lookup_id,
|
||||
const char *name, const char *const *parent_names,
|
||||
u8 num_parents,
|
||||
const struct rockchip_cpuclk_reg_data *reg_data,
|
||||
const struct rockchip_cpuclk_rate_table *rates,
|
||||
int nrates)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
@ -588,9 +592,10 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
||||
|
||||
rockchip_clk_add_lookup(ctx, clk, lookup_id);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
|
||||
|
||||
void __init rockchip_clk_protect_critical(const char *const clocks[],
|
||||
int nclocks)
|
||||
void rockchip_clk_protect_critical(const char *const clocks[],
|
||||
int nclocks)
|
||||
{
|
||||
int i;
|
||||
|
||||
@ -602,6 +607,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
|
||||
clk_prepare_enable(clk);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);
|
||||
|
||||
static void __iomem *rst_base;
|
||||
static unsigned int reg_restart;
|
||||
@ -621,10 +627,10 @@ static struct notifier_block rockchip_restart_handler = {
|
||||
.priority = 128,
|
||||
};
|
||||
|
||||
void __init
|
||||
void
|
||||
rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
|
||||
unsigned int reg,
|
||||
void (*cb)(void))
|
||||
unsigned int reg,
|
||||
void (*cb)(void))
|
||||
{
|
||||
int ret;
|
||||
|
||||
@ -636,3 +642,4 @@ rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
|
||||
pr_err("%s: cannot register restart handler, %d\n",
|
||||
__func__, ret);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier);
|
||||
|
||||
@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
|
||||
.deassert = rockchip_softrst_deassert,
|
||||
};
|
||||
|
||||
void __init rockchip_register_softrst(struct device_node *np,
|
||||
unsigned int num_regs,
|
||||
void __iomem *base, u8 flags)
|
||||
void rockchip_register_softrst(struct device_node *np,
|
||||
unsigned int num_regs,
|
||||
void __iomem *base, u8 flags)
|
||||
{
|
||||
struct rockchip_softrst *softrst;
|
||||
int ret;
|
||||
@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node *np,
|
||||
kfree(softrst);
|
||||
}
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(rockchip_register_softrst);
|
||||
|
||||
@ -126,7 +126,7 @@ static int tegra210_clk_emc_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
if (!provider || !provider->configs || provider->num_configs == 0)
|
||||
if (!provider->configs || provider->num_configs == 0)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < provider->num_configs; i++) {
|
||||
|
||||
@ -82,7 +82,12 @@ static int _omap2_clk_allow_idle(struct clk_hw_omap *clk)
|
||||
*/
|
||||
int omap2_clk_deny_idle(struct clk *clk)
|
||||
{
|
||||
struct clk_hw *hw = __clk_get_hw(clk);
|
||||
struct clk_hw *hw;
|
||||
|
||||
if (!clk)
|
||||
return -EINVAL;
|
||||
|
||||
hw = __clk_get_hw(clk);
|
||||
|
||||
if (omap2_clk_is_hw_omap(hw)) {
|
||||
struct clk_hw_omap *c = to_clk_hw_omap(hw);
|
||||
@ -101,7 +106,12 @@ int omap2_clk_deny_idle(struct clk *clk)
|
||||
*/
|
||||
int omap2_clk_allow_idle(struct clk *clk)
|
||||
{
|
||||
struct clk_hw *hw = __clk_get_hw(clk);
|
||||
struct clk_hw *hw;
|
||||
|
||||
if (!clk)
|
||||
return -EINVAL;
|
||||
|
||||
hw = __clk_get_hw(clk);
|
||||
|
||||
if (omap2_clk_is_hw_omap(hw)) {
|
||||
struct clk_hw_omap *c = to_clk_hw_omap(hw);
|
||||
|
||||
@ -637,6 +637,7 @@ static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst
|
||||
{ DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
|
||||
{ DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
|
||||
{ DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
|
||||
{ DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
||||
@ -148,10 +148,12 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
|
||||
if (!omap2_clk_is_hw_omap(clk_hw)) {
|
||||
pr_warn("can't setup clkdm for basic clk %s\n",
|
||||
__clk_get_name(clk));
|
||||
clk_put(clk);
|
||||
continue;
|
||||
}
|
||||
to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
|
||||
omap2_init_clk_clkdm(clk_hw);
|
||||
clk_put(clk);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -332,6 +332,7 @@
|
||||
#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
|
||||
#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
|
||||
#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
|
||||
#define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8)
|
||||
|
||||
/* l4per2 clocks */
|
||||
#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc
|
||||
|
||||
131
include/dt-bindings/clock/mt8167-clk.h
Normal file
131
include/dt-bindings/clock/mt8167-clk.h
Normal file
@ -0,0 +1,131 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
* Copyright (c) 2020 BayLibre, SAS.
|
||||
* Author: James Liao <jamesjj.liao@mediatek.com>
|
||||
* Fabien Parent <fparent@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT8167_H
|
||||
#define _DT_BINDINGS_CLK_MT8167_H
|
||||
|
||||
/* MT8167 is based on MT8516 */
|
||||
#include <dt-bindings/clock/mt8516-clk.h>
|
||||
|
||||
/* APMIXEDSYS */
|
||||
|
||||
#define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0)
|
||||
#define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1)
|
||||
#define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2)
|
||||
#define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3)
|
||||
|
||||
/* TOPCKGEN */
|
||||
|
||||
#define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0)
|
||||
#define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1)
|
||||
#define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2)
|
||||
#define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3)
|
||||
#define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4)
|
||||
#define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5)
|
||||
#define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6)
|
||||
#define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7)
|
||||
#define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8)
|
||||
#define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9)
|
||||
#define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10)
|
||||
#define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11)
|
||||
#define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12)
|
||||
#define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13)
|
||||
#define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14)
|
||||
#define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15)
|
||||
#define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16)
|
||||
#define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17)
|
||||
#define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18)
|
||||
#define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19)
|
||||
#define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20)
|
||||
#define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21)
|
||||
#define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22)
|
||||
#define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23)
|
||||
#define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24)
|
||||
#define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25)
|
||||
#define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26)
|
||||
#define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27)
|
||||
#define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28)
|
||||
#define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29)
|
||||
#define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30)
|
||||
#define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31)
|
||||
#define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32)
|
||||
#define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33)
|
||||
#define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34)
|
||||
#define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35)
|
||||
#define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36)
|
||||
#define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37)
|
||||
#define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38)
|
||||
#define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39)
|
||||
#define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40)
|
||||
#define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41)
|
||||
#define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42)
|
||||
#define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43)
|
||||
|
||||
/* MFGCFG */
|
||||
|
||||
#define CLK_MFG_BAXI 0
|
||||
#define CLK_MFG_BMEM 1
|
||||
#define CLK_MFG_BG3D 2
|
||||
#define CLK_MFG_B26M 3
|
||||
#define CLK_MFG_NR_CLK 4
|
||||
|
||||
/* MMSYS */
|
||||
|
||||
#define CLK_MM_SMI_COMMON 0
|
||||
#define CLK_MM_SMI_LARB0 1
|
||||
#define CLK_MM_CAM_MDP 2
|
||||
#define CLK_MM_MDP_RDMA 3
|
||||
#define CLK_MM_MDP_RSZ0 4
|
||||
#define CLK_MM_MDP_RSZ1 5
|
||||
#define CLK_MM_MDP_TDSHP 6
|
||||
#define CLK_MM_MDP_WDMA 7
|
||||
#define CLK_MM_MDP_WROT 8
|
||||
#define CLK_MM_FAKE_ENG 9
|
||||
#define CLK_MM_DISP_OVL0 10
|
||||
#define CLK_MM_DISP_RDMA0 11
|
||||
#define CLK_MM_DISP_RDMA1 12
|
||||
#define CLK_MM_DISP_WDMA 13
|
||||
#define CLK_MM_DISP_COLOR 14
|
||||
#define CLK_MM_DISP_CCORR 15
|
||||
#define CLK_MM_DISP_AAL 16
|
||||
#define CLK_MM_DISP_GAMMA 17
|
||||
#define CLK_MM_DISP_DITHER 18
|
||||
#define CLK_MM_DISP_UFOE 19
|
||||
#define CLK_MM_DISP_PWM_MM 20
|
||||
#define CLK_MM_DISP_PWM_26M 21
|
||||
#define CLK_MM_DSI_ENGINE 22
|
||||
#define CLK_MM_DSI_DIGITAL 23
|
||||
#define CLK_MM_DPI0_ENGINE 24
|
||||
#define CLK_MM_DPI0_PXL 25
|
||||
#define CLK_MM_LVDS_PXL 26
|
||||
#define CLK_MM_LVDS_CTS 27
|
||||
#define CLK_MM_DPI1_ENGINE 28
|
||||
#define CLK_MM_DPI1_PXL 29
|
||||
#define CLK_MM_HDMI_PXL 30
|
||||
#define CLK_MM_HDMI_SPDIF 31
|
||||
#define CLK_MM_HDMI_ADSP_BCK 32
|
||||
#define CLK_MM_HDMI_PLL 33
|
||||
#define CLK_MM_NR_CLK 34
|
||||
|
||||
/* IMGSYS */
|
||||
|
||||
#define CLK_IMG_LARB1_SMI 0
|
||||
#define CLK_IMG_CAM_SMI 1
|
||||
#define CLK_IMG_CAM_CAM 2
|
||||
#define CLK_IMG_SEN_TG 3
|
||||
#define CLK_IMG_SEN_CAM 4
|
||||
#define CLK_IMG_VENC 5
|
||||
#define CLK_IMG_NR_CLK 6
|
||||
|
||||
/* VDECSYS */
|
||||
|
||||
#define CLK_VDEC_CKEN 0
|
||||
#define CLK_VDEC_LARB1_CKEN 1
|
||||
#define CLK_VDEC_NR_CLK 2
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8167_H */
|
||||
Loading…
Reference in New Issue
Block a user