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https://github.com/edk2-porting/linux-next.git
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powerpc/powernv: Fix endian issues in powernv PCI code
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
parent
81063cdd61
commit
3a1a46612d
@ -457,7 +457,7 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
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static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
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u64 *startp, u64 *endp)
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{
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u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
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__be64 __iomem *invalidate = (__be64 __iomem *)tbl->it_index;
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unsigned long start, end, inc;
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start = __pa(startp);
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@ -484,7 +484,7 @@ static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
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mb(); /* Ensure above stores are visible */
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while (start <= end) {
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__raw_writeq(start, invalidate);
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__raw_writeq(cpu_to_be64(start), invalidate);
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start += inc;
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}
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@ -499,7 +499,7 @@ static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
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u64 *startp, u64 *endp)
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{
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unsigned long start, end, inc;
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u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
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__be64 __iomem *invalidate = (__be64 __iomem *)tbl->it_index;
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/* We'll invalidate DMA address in PE scope */
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start = 0x2ul << 60;
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@ -515,7 +515,7 @@ static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
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mb();
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while (start <= end) {
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__raw_writeq(start, invalidate);
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__raw_writeq(cpu_to_be64(start), invalidate);
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start += inc;
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}
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}
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@ -786,8 +786,7 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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struct irq_data *idata;
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struct irq_chip *ichip;
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unsigned int xive_num = hwirq - phb->msi_base;
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uint64_t addr64;
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uint32_t addr32, data;
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__be32 data;
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int rc;
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/* No PE assigned ? bail out ... no MSI for you ! */
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@ -811,6 +810,8 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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}
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if (is_64) {
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__be64 addr64;
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rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
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&addr64, &data);
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if (rc) {
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@ -818,9 +819,11 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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pci_name(dev), rc);
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return -EIO;
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}
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msg->address_hi = addr64 >> 32;
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msg->address_lo = addr64 & 0xfffffffful;
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msg->address_hi = be64_to_cpu(addr64) >> 32;
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msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
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} else {
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__be32 addr32;
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rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
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&addr32, &data);
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if (rc) {
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@ -829,9 +832,9 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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return -EIO;
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}
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msg->address_hi = 0;
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msg->address_lo = addr32;
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msg->address_lo = be32_to_cpu(addr32);
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}
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msg->data = data;
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msg->data = be32_to_cpu(data);
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/*
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* Change the IRQ chip for the MSI interrupts on PHB3.
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@ -1107,7 +1110,7 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
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struct pnv_phb *phb;
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unsigned long size, m32map_off, iomap_off, pemap_off;
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const __be64 *prop64;
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const u32 *prop32;
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const __be32 *prop32;
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int len;
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u64 phb_id;
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void *aux;
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@ -1142,8 +1145,8 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
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spin_lock_init(&phb->lock);
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prop32 = of_get_property(np, "bus-range", &len);
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if (prop32 && len == 8) {
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hose->first_busno = prop32[0];
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hose->last_busno = prop32[1];
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hose->first_busno = be32_to_cpu(prop32[0]);
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hose->last_busno = be32_to_cpu(prop32[1]);
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} else {
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pr_warn(" Broken <bus-range> on %s\n", np->full_name);
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hose->first_busno = 0;
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@ -1175,7 +1178,7 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
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if (!prop32)
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phb->ioda.total_pe = 1;
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else
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phb->ioda.total_pe = *prop32;
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phb->ioda.total_pe = be32_to_cpup(prop32);
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phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
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/* FW Has already off top 64k of M32 space (MSI space) */
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@ -236,7 +236,7 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
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{
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s64 rc;
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u8 fstate;
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u16 pcierr;
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__be16 pcierr;
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u32 pe_no;
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/*
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@ -283,16 +283,16 @@ int pnv_pci_cfg_read(struct device_node *dn,
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break;
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}
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case 2: {
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u16 v16;
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__be16 v16;
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rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
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&v16);
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*val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
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*val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
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break;
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}
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case 4: {
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u32 v32;
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__be32 v32;
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rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
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*val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
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*val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
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break;
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}
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default:
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@ -404,7 +404,7 @@ static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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struct dma_attrs *attrs)
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{
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u64 proto_tce;
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u64 *tcep, *tces;
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__be64 *tcep, *tces;
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u64 rpn;
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proto_tce = TCE_PCI_READ; // Read allowed
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@ -416,7 +416,7 @@ static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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rpn = __pa(uaddr) >> TCE_SHIFT;
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while (npages--)
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*(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
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*(tcep++) = cpu_to_be64(proto_tce | (rpn++ << TCE_RPN_SHIFT));
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/* Some implementations won't cache invalid TCEs and thus may not
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* need that flush. We'll probably turn it_type into a bit mask
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@ -430,12 +430,12 @@ static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
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{
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u64 *tcep, *tces;
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__be64 *tcep, *tces;
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tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
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while (npages--)
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*(tcep++) = 0;
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*(tcep++) = cpu_to_be64(0);
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if (tbl->it_type & TCE_PCI_SWINV_FREE)
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pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
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@ -462,8 +462,8 @@ void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
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{
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struct iommu_table *tbl;
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const __be64 *basep;
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const __be32 *sizep, *swinvp;
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const __be64 *basep, *swinvp;
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const __be32 *sizep;
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basep = of_get_property(hose->dn, "linux,tce-base", NULL);
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sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
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@ -484,9 +484,8 @@ static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
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swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
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NULL);
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if (swinvp) {
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tbl->it_busno = of_read_ulong(&swinvp[1], 2);
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tbl->it_index =
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(unsigned long)ioremap(of_read_number(swinvp, 2), 8);
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tbl->it_busno = swinvp[1];
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tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
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tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
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}
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return tbl;
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