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drm: extract drm_dp_max_lane_count helper
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -124,19 +124,6 @@ intel_edp_target_clock(struct intel_encoder *intel_encoder,
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return mode->clock;
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}
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static int
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intel_dp_max_lane_count(struct intel_dp *intel_dp)
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{
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int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
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switch (max_lane_count) {
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case 1: case 2: case 4:
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break;
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default:
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max_lane_count = 4;
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}
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return max_lane_count;
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}
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static int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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@ -197,7 +184,7 @@ intel_dp_adjust_dithering(struct intel_dp *intel_dp,
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bool adjust_mode)
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{
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int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
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int max_lanes = intel_dp_max_lane_count(intel_dp);
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int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
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int max_rate, mode_rate;
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mode_rate = intel_dp_link_required(mode->clock, 24);
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@ -699,7 +686,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder,
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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struct intel_connector *intel_connector = intel_dp->attached_connector;
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int lane_count, clock;
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int max_lane_count = intel_dp_max_lane_count(intel_dp);
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int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
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int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
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int bpp, mode_rate;
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static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
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@ -347,11 +347,6 @@ static int dp_get_max_dp_pix_clock(int link_rate,
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return (link_rate * lane_num * 8) / bpp;
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}
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static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
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{
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return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
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}
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/***** radeon specific DP functions *****/
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/* First get the min lane# when low rate is used according to pixel clock
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@ -364,7 +359,7 @@ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
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{
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int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
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int max_link_rate = drm_dp_max_link_rate(dpcd);
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int max_lane_num = dp_get_max_lane_number(dpcd);
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int max_lane_num = drm_dp_max_lane_count(dpcd);
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int lane_num;
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int max_dp_pix_clock;
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@ -346,4 +346,11 @@ drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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{
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return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
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}
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static inline u8
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drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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{
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return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
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}
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#endif /* _DRM_DP_HELPER_H_ */
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