mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-04 11:43:54 +08:00
Merge branch 'pci/dpc' into next
* pci/dpc: PCI/DPC: Reformat DPC register definitions PCI/DPC: Add and use DPC Status register field definitions PCI/DPC: Squash dpc_rp_pio_get_info() into dpc_process_rp_pio_error() PCI/DPC: Remove unnecessary RP PIO register structs PCI/DPC: Push dpc->rp_pio_status assignment into dpc_rp_pio_get_info() PCI/DPC: Squash dpc_rp_pio_print_error() into dpc_rp_pio_get_info() PCI/DPC: Make RP PIO log size check more generic PCI/DPC: Rename local "status" to "dpc_status" PCI/DPC: Squash dpc_rp_pio_print_tlp_header() into dpc_rp_pio_print_error() PCI/DPC: Process RP PIO details only if RP PIO extensions supported PCI/DPC: Read RP PIO Log Size once at probe PCI/DPC: Rename struct dpc_dev.rp to rp_extensions PCI/DPC: Add local variable for DPC capability offset PCI/DPC: Rename interrupt_event_handler() to dpc_work() PCI/DPC: Fix interrupt message number print PCI/DPC: Enable DPC only if AER is available PCI/DPC: Fix shared interrupt handling
This commit is contained in:
Bjorn Helgaas
Bjorn Helgaas
commit
3972b0e2c2
@ -92,7 +92,7 @@ config PCIE_PME
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config PCIE_DPC
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bool "PCIe Downstream Port Containment support"
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depends on PCIEPORTBUS
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depends on PCIEPORTBUS && PCIEAER
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default n
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help
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This enables PCI Express Downstream Port Containment (DPC)
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@ -15,34 +15,15 @@
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#include <linux/pci.h>
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#include <linux/pcieport_if.h>
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#include "../pci.h"
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struct rp_pio_header_log_regs {
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u32 dw0;
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u32 dw1;
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u32 dw2;
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u32 dw3;
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};
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struct dpc_rp_pio_regs {
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u32 status;
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u32 mask;
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u32 severity;
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u32 syserror;
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u32 exception;
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struct rp_pio_header_log_regs header_log;
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u32 impspec_log;
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u32 tlp_prefix_log[4];
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u32 log_size;
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u16 first_error;
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};
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#include "aer/aerdrv.h"
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struct dpc_dev {
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struct pcie_device *dev;
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struct work_struct work;
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int cap_pos;
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bool rp;
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u16 cap_pos;
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bool rp_extensions;
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u32 rp_pio_status;
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u8 rp_log_size;
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};
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static const char * const rp_pio_error_string[] = {
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@ -72,13 +53,13 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
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unsigned long timeout = jiffies + HZ;
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struct pci_dev *pdev = dpc->dev->port;
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struct device *dev = &dpc->dev->device;
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u16 status;
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u16 cap = dpc->cap_pos, status;
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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while (status & PCI_EXP_DPC_RP_BUSY &&
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!time_after(jiffies, timeout)) {
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msleep(10);
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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}
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if (status & PCI_EXP_DPC_RP_BUSY) {
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dev_warn(dev, "DPC root port still busy\n");
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@ -104,11 +85,12 @@ static void dpc_wait_link_inactive(struct dpc_dev *dpc)
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dev_warn(dev, "Link state not disabled for DPC event\n");
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}
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static void interrupt_event_handler(struct work_struct *work)
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static void dpc_work(struct work_struct *work)
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{
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struct dpc_dev *dpc = container_of(work, struct dpc_dev, work);
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struct pci_dev *dev, *temp, *pdev = dpc->dev->port;
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struct pci_bus *parent = pdev->subordinate;
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u16 cap = dpc->cap_pos, ctl;
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pci_lock_rescan_remove();
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list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
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@ -124,124 +106,77 @@ static void interrupt_event_handler(struct work_struct *work)
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pci_unlock_rescan_remove();
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dpc_wait_link_inactive(dpc);
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if (dpc->rp && dpc_wait_rp_inactive(dpc))
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if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
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return;
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if (dpc->rp && dpc->rp_pio_status) {
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pci_write_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
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dpc->rp_pio_status);
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if (dpc->rp_extensions && dpc->rp_pio_status) {
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pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS,
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dpc->rp_pio_status);
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dpc->rp_pio_status = 0;
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}
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pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS,
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pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
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PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
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}
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static void dpc_rp_pio_print_tlp_header(struct device *dev,
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struct rp_pio_header_log_regs *t)
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{
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dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
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t->dw0, t->dw1, t->dw2, t->dw3);
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}
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static void dpc_rp_pio_print_error(struct dpc_dev *dpc,
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struct dpc_rp_pio_regs *rp_pio)
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{
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struct device *dev = &dpc->dev->device;
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int i;
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u32 status;
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dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
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rp_pio->status, rp_pio->mask);
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dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
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rp_pio->severity, rp_pio->syserror, rp_pio->exception);
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status = (rp_pio->status & ~rp_pio->mask);
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for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
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if (!(status & (1 << i)))
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continue;
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dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
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rp_pio->first_error == i ? " (First)" : "");
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}
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dpc_rp_pio_print_tlp_header(dev, &rp_pio->header_log);
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if (rp_pio->log_size == 4)
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return;
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dev_err(dev, "RP PIO ImpSpec Log %#010x\n", rp_pio->impspec_log);
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for (i = 0; i < rp_pio->log_size - 5; i++)
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dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i,
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rp_pio->tlp_prefix_log[i]);
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}
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static void dpc_rp_pio_get_info(struct dpc_dev *dpc,
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struct dpc_rp_pio_regs *rp_pio)
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{
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struct pci_dev *pdev = dpc->dev->port;
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struct device *dev = &dpc->dev->device;
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int i;
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u16 cap;
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u16 status;
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
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&rp_pio->status);
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_MASK,
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&rp_pio->mask);
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SEVERITY,
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&rp_pio->severity);
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SYSERROR,
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&rp_pio->syserror);
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pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_EXCEPTION,
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&rp_pio->exception);
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/* Get First Error Pointer */
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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rp_pio->first_error = (status & 0x1f00) >> 8;
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
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rp_pio->log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
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if (rp_pio->log_size < 4 || rp_pio->log_size > 9) {
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dev_err(dev, "RP PIO log size %u is invalid\n",
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rp_pio->log_size);
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return;
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}
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
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&rp_pio->header_log.dw0);
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
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&rp_pio->header_log.dw1);
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
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&rp_pio->header_log.dw2);
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
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&rp_pio->header_log.dw3);
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if (rp_pio->log_size == 4)
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return;
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG,
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&rp_pio->impspec_log);
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for (i = 0; i < rp_pio->log_size - 5; i++)
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pci_read_config_dword(pdev,
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dpc->cap_pos + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
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&rp_pio->tlp_prefix_log[i]);
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
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pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
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ctl | PCI_EXP_DPC_CTL_INT_EN);
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}
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static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
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{
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struct dpc_rp_pio_regs rp_pio_regs;
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struct device *dev = &dpc->dev->device;
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struct pci_dev *pdev = dpc->dev->port;
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u16 cap = dpc->cap_pos, dpc_status, first_error;
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u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
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int i;
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dpc_rp_pio_get_info(dpc, &rp_pio_regs);
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dpc_rp_pio_print_error(dpc, &rp_pio_regs);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
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dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
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status, mask);
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dpc->rp_pio_status = rp_pio_regs.status;
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dpc->rp_pio_status = status;
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
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dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
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sev, syserr, exc);
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/* Get First Error Pointer */
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
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first_error = (dpc_status & 0x1f00) >> 8;
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status &= ~mask;
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for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
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if (status & (1 << i))
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dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
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first_error == i ? " (First)" : "");
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}
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if (dpc->rp_log_size < 4)
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return;
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
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&dw0);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
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&dw1);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
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&dw2);
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
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&dw3);
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dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
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dw0, dw1, dw2, dw3);
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if (dpc->rp_log_size < 5)
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return;
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pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
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dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
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for (i = 0; i < dpc->rp_log_size - 5; i++) {
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pci_read_config_dword(pdev,
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cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
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dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
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}
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}
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static irqreturn_t dpc_irq(int irq, void *context)
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@ -249,34 +184,49 @@ static irqreturn_t dpc_irq(int irq, void *context)
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struct dpc_dev *dpc = (struct dpc_dev *)context;
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struct pci_dev *pdev = dpc->dev->port;
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struct device *dev = &dpc->dev->device;
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u16 status, source;
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u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason;
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_SOURCE_ID,
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&source);
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if (!status || status == (u16)(~0))
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
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if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0))
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return IRQ_NONE;
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
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if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT))
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return IRQ_NONE;
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if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) {
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pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
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PCI_EXP_DPC_STATUS_INTERRUPT);
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return IRQ_HANDLED;
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}
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pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
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ctl & ~PCI_EXP_DPC_CTL_INT_EN);
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pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID,
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&source);
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dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
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status, source);
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if (status & PCI_EXP_DPC_STATUS_TRIGGER) {
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u16 reason = (status >> 1) & 0x3;
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u16 ext_reason = (status >> 5) & 0x3;
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reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
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ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
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dev_warn(dev, "DPC %s detected, remove downstream devices\n",
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(reason == 0) ? "unmasked uncorrectable error" :
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(reason == 1) ? "ERR_NONFATAL" :
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(reason == 2) ? "ERR_FATAL" :
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(ext_reason == 0) ? "RP PIO error" :
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(ext_reason == 1) ? "software trigger" :
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"reserved error");
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/* show RP PIO error detail information */
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if (reason == 3 && ext_reason == 0)
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dpc_process_rp_pio_error(dpc);
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dev_warn(dev, "DPC %s detected, remove downstream devices\n",
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(reason == 0) ? "unmasked uncorrectable error" :
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(reason == 1) ? "ERR_NONFATAL" :
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(reason == 2) ? "ERR_FATAL" :
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(ext_reason == 0) ? "RP PIO error" :
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(ext_reason == 1) ? "software trigger" :
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"reserved error");
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/* show RP PIO error detail information */
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if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
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dpc_process_rp_pio_error(dpc);
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schedule_work(&dpc->work);
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schedule_work(&dpc->work);
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}
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return IRQ_HANDLED;
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}
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@ -289,13 +239,16 @@ static int dpc_probe(struct pcie_device *dev)
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int status;
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u16 ctl, cap;
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if (pcie_aer_get_firmware_first(pdev))
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return -ENOTSUPP;
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dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
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if (!dpc)
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return -ENOMEM;
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dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
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dpc->dev = dev;
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INIT_WORK(&dpc->work, interrupt_event_handler);
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INIT_WORK(&dpc->work, dpc_work);
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set_service_data(dev, dpc);
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status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
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@ -309,15 +262,23 @@ static int dpc_probe(struct pcie_device *dev)
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
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dpc->rp = (cap & PCI_EXP_DPC_CAP_RP_EXT);
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dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
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if (dpc->rp_extensions) {
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dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
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if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
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dev_err(device, "RP PIO log size %u is invalid\n",
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dpc->rp_log_size);
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dpc->rp_log_size = 0;
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}
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}
|
||||
|
||||
ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
|
||||
pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
|
||||
|
||||
dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
|
||||
cap & 0xf, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
|
||||
cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
|
||||
FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
|
||||
FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), (cap >> 8) & 0xf,
|
||||
FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
|
||||
FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -216,9 +216,9 @@ static int get_port_device_capability(struct pci_dev *dev)
|
||||
return 0;
|
||||
|
||||
cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP
|
||||
| PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;
|
||||
| PCIE_PORT_SERVICE_VC;
|
||||
if (pci_aer_available())
|
||||
cap_mask |= PCIE_PORT_SERVICE_AER;
|
||||
cap_mask |= PCIE_PORT_SERVICE_AER | PCIE_PORT_SERVICE_DPC;
|
||||
|
||||
if (pcie_ports_auto)
|
||||
pcie_port_platform_notify(dev, &cap_mask);
|
||||
|
||||
@ -966,26 +966,28 @@
|
||||
|
||||
/* Downstream Port Containment */
|
||||
#define PCI_EXP_DPC_CAP 4 /* DPC Capability */
|
||||
#define PCI_EXP_DPC_IRQ 0x1f /* DPC Interrupt Message Number */
|
||||
#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */
|
||||
#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */
|
||||
#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */
|
||||
#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */
|
||||
#define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */
|
||||
#define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */
|
||||
#define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */
|
||||
#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */
|
||||
#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */
|
||||
#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
|
||||
|
||||
#define PCI_EXP_DPC_CTL 6 /* DPC control */
|
||||
#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 /* Enable trigger on ERR_NONFATAL message */
|
||||
#define PCI_EXP_DPC_CTL_INT_EN 0x08 /* DPC Interrupt Enable */
|
||||
#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
|
||||
#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
|
||||
|
||||
#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
|
||||
#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 /* Trigger Status */
|
||||
#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 /* Interrupt Status */
|
||||
#define PCI_EXP_DPC_RP_BUSY 0x10 /* Root Port Busy */
|
||||
#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */
|
||||
#define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */
|
||||
#define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */
|
||||
#define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */
|
||||
#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */
|
||||
|
||||
#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
|
||||
|
||||
#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */
|
||||
#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO MASK */
|
||||
#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO Mask */
|
||||
#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */
|
||||
#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */
|
||||
#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user