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https://github.com/edk2-porting/linux-next.git
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net: mvpp2: initialize the GMAC when using a port
This adds a routine to initialize the GMAC at the port level when using a port. This wasn't done until this commit, and the mvpp2 driver was relying on the bootloader/firmware initialization. This doesn't mean everything is configured in the mvpp2 driver now, but it helps reducing the gap. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
2055d6268d
commit
3919357fb0
@ -315,6 +315,7 @@
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/* Per-port registers */
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#define MVPP2_GMAC_CTRL_0_REG 0x0
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#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
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#define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
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#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
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#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
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#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
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@ -326,16 +327,21 @@
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#define MVPP2_GMAC_SA_LOW_OFFS 7
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#define MVPP2_GMAC_CTRL_2_REG 0x8
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#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
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#define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1)
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#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
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#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
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#define MVPP2_GMAC_DISABLE_PADDING BIT(5)
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#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
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#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
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#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
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#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
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#define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2)
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#define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3)
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#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
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#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
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#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
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#define MVPP2_GMAC_FC_ADV_EN BIT(9)
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#define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)
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#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
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#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
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#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
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@ -4245,6 +4251,92 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
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/* Port configuration routines */
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static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
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{
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u32 val;
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if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
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val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL |
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MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
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val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
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writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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val |= MVPP2_GMAC_DISABLE_PADDING;
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val &= ~MVPP2_GMAC_FLOW_CTRL_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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} else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
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val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
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MVPP22_CTRL4_SYNC_BYPASS_DIS |
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MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
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val &= ~MVPP22_CTRL4_DP_CLK_SEL;
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writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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val &= ~MVPP2_GMAC_DISABLE_PADDING;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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}
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/* The port is connected to a copper PHY */
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val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
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val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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val |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
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MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
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MVPP2_GMAC_AN_DUPLEX_EN;
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if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
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val |= MVPP2_GMAC_IN_BAND_AUTONEG;
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)
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{
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u32 val;
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/* Force link down */
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val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
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val |= MVPP2_GMAC_FORCE_LINK_DOWN;
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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/* Set the GMAC in a reset state */
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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val |= MVPP2_GMAC_PORT_RESET_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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/* Configure the PCS and in-band AN */
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
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} else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
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val |= MVPP2_GMAC_PORT_RGMII_MASK;
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}
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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mvpp2_port_mii_gmac_configure_mode(port);
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/* Unset the GMAC reset state */
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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val &= ~MVPP2_GMAC_PORT_RESET_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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/* Stop forcing link down */
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val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static void mvpp22_port_mii_set(struct mvpp2_port *port)
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{
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u32 val;
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@ -4262,38 +4354,19 @@ static void mvpp22_port_mii_set(struct mvpp2_port *port)
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writel(val, port->base + MVPP22_XLG_CTRL3_REG);
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}
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val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
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if (port->phy_interface == PHY_INTERFACE_MODE_RGMII)
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val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL;
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else
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val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
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val &= ~MVPP22_CTRL4_DP_CLK_SEL;
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val |= MVPP22_CTRL4_SYNC_BYPASS_DIS;
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val |= MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
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writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
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}
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static void mvpp2_port_mii_set(struct mvpp2_port *port)
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{
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u32 val;
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if (port->priv->hw_version == MVPP22)
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mvpp22_port_mii_set(port);
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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switch (port->phy_interface) {
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case PHY_INTERFACE_MODE_SGMII:
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val |= MVPP2_GMAC_INBAND_AN_MASK;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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val |= MVPP2_GMAC_PORT_RGMII_MASK;
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default:
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val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
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}
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII)
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mvpp2_port_mii_gmac_configure(port);
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}
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static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
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