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clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
Add a clock type and macro for defining clocks using the OSC EXTAL predivider combined with a fixed divider. On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and thus must be specified in the configuration structure. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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@ -563,6 +563,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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return cpg_z_clk_register(core->name, __clk_get_name(parent),
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base, CPG_FRQCRC_Z2FC_MASK);
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case CLK_TYPE_GEN3_OSC:
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/*
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* Clock combining OSC EXTAL predivider and a fixed divider
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*/
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div = cpg_pll_config->osc_prediv * core->div;
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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@ -23,6 +23,7 @@ enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_PE,
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CLK_TYPE_GEN3_Z,
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CLK_TYPE_GEN3_Z2,
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CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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@ -33,6 +34,8 @@ enum rcar_gen3_clk_types {
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
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(_parent_sscg) << 16 | (_parent_clean), \
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.div = (_div_sscg) << 16 | (_div_clean))
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#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
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struct rcar_gen3_cpg_pll_config {
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u8 extal_div;
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@ -40,6 +43,7 @@ struct rcar_gen3_cpg_pll_config {
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u8 pll1_div;
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u8 pll3_mult;
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u8 pll3_div;
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u8 osc_prediv;
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};
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#define CPG_RCKCR 0x240
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