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MIPS: PCI: remember nasid changed by set interrupt affinity

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When changing interrupt affinity remember the possible changed nasid,
otherwise an interrupt deactivate/activate sequence will incorrectly
setup interrupt.

Fixes: e6308b6d35 ("MIPS: SGI-IP27: abstract chipset irq from bridge")
Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Thomas Bogendoerfer 2019-11-19 12:08:57 +01:00 committed by Paul Burton
parent e3d765a941
commit 37640adbef
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GPG Key ID: 3EA79FACB57500DD
1 changed files with 2 additions and 3 deletions
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5
arch/mips/pci/pci-xtalk-bridge.c
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@ -306,16 +306,15 @@ static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
struct bridge_irq_chip_data *data = d->chip_data;
int bit = d->parent_data->hwirq;
int pin = d->hwirq;
nasid_t nasid;
int ret, cpu;
ret = irq_chip_set_affinity_parent(d, mask, force);
if (ret >= 0) {
cpu = cpumask_first_and(mask, cpu_online_mask);
nasid = cpu_to_node(cpu);
data->nasid = cpu_to_node(cpu);
bridge_write(data->bc, b_int_addr[pin].addr,
(((data->bc->intr_addr >> 30) & 0x30000) |
bit | (nasid << 8)));
bit | (data->nasid << 8)));
bridge_read(data->bc, b_wid_tflush);
}
return ret;