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iommu/mediatek: Add sub_comm id in translation fault
The max larb number that a iommu HW support is 8(larb0~larb7 in the below diagram). If the larb's number is over 8, we use a sub_common for merging several larbs into one larb. At this case, we will extend larb_id: bit[11:9] means common-id; bit[8:7] means subcommon-id; >From these two variables, we could get the real larb number when translation fault happen. The diagram is as below: EMI | IOMMU | ----------------- | | common1 common0 | | ----------------- | smi common | ------------------------------------ | | | | | | 3'd0 3'd1 3'd2 3'd3 ... 3'd7 <-common_id(max is 8) | | | | | | Larb0 Larb1 | Larb3 ... Larb7 | smi sub common | -------------------------- | | | | 2'd0 2'd1 2'd2 2'd3 <-sub_common_id(max is 4) | | | | Larb8 Larb9 Larb10 Larb11 In this patch we extend larb_remap[] to larb_remap[8][4] for this. larb_remap[x][y]: x means common-id above, y means subcommon_id above. We can also distinguish if the M4U HW has sub_common by HAS_SUB_COMM macro. Signed-off-by: Chao Hao <chao.hao@mediatek.com> Reviewed-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20200703044127.27438-7-chao.hao@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -91,6 +91,8 @@
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#define REG_MMU1_INVLD_PA 0x148
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#define REG_MMU0_INT_ID 0x150
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#define REG_MMU1_INT_ID 0x154
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#define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)
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#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
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#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
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#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
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@ -109,6 +111,7 @@
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#define HAS_VLD_PA_RNG BIT(2)
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#define RESET_AXI BIT(3)
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#define OUT_ORDER_WR_EN BIT(4)
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#define HAS_SUB_COMM BIT(5)
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#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
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((((pdata)->flags) & (_x)) == (_x))
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@ -239,7 +242,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
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struct mtk_iommu_data *data = dev_id;
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struct mtk_iommu_domain *dom = data->m4u_dom;
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u32 int_state, regval, fault_iova, fault_pa;
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unsigned int fault_larb, fault_port;
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unsigned int fault_larb, fault_port, sub_comm = 0;
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bool layer, write;
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/* Read error info from registers */
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@ -255,10 +258,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
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}
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layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
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write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
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fault_larb = F_MMU_INT_ID_LARB_ID(regval);
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fault_port = F_MMU_INT_ID_PORT_ID(regval);
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fault_larb = data->plat_data->larbid_remap[fault_larb];
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if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
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fault_larb = F_MMU_INT_ID_COMM_ID(regval);
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sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
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} else {
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fault_larb = F_MMU_INT_ID_LARB_ID(regval);
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}
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fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
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if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
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write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
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@ -785,21 +792,21 @@ static const struct mtk_iommu_plat_data mt2712_data = {
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.m4u_plat = M4U_MT2712,
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.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
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.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
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};
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static const struct mtk_iommu_plat_data mt8173_data = {
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.m4u_plat = M4U_MT8173,
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.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
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.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
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};
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static const struct mtk_iommu_plat_data mt8183_data = {
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.m4u_plat = M4U_MT8183,
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.flags = RESET_AXI,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
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.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
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};
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static const struct of_device_id mtk_iommu_of_ids[] = {
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@ -17,6 +17,9 @@
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#include <linux/spinlock.h>
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#include <soc/mediatek/smi.h>
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#define MTK_LARB_COM_MAX 8
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#define MTK_LARB_SUBCOM_MAX 4
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struct mtk_iommu_suspend_reg {
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union {
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u32 standard_axi_mode;/* v1 */
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@ -41,7 +44,7 @@ struct mtk_iommu_plat_data {
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enum mtk_iommu_plat m4u_plat;
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u32 flags;
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u32 inv_sel_reg;
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unsigned char larbid_remap[MTK_LARB_NR_MAX];
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unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
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};
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struct mtk_iommu_domain;
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