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Renesas ARM Based SoC r8a7778 CCF and Multiplatform Updates for v4.1
* Add CCF and them multiplatform support to r8a7778 SoC and its bockw board. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJU9671AAoJENfPZGlqN0++71UP/iuiuiyeF3Wgqc9Pu22hVg8g 3qd0Hqw2iUx07KV29kGoJmAkL48A5zGOk/JqvLY2BX5+ZAdWxy4sbY/njMzeUAH6 hRiZGbgb+7gRSsQNCbxmR6Kh1zx8akxrQOw7PzJs0Yjwh2I8+rrb+2qxDNy1RbO9 KoTYk4j98mOLdwfGYixoVjSIdgt70JNKUn3LY0JHn6Ss38u/1zDB55PnlXeCKNfu t7WSwTxbdN1h0hJ03y3ZsTQMVb3BDYMfRFtWZCZ/AE4CFM53oeRVkXEewbPfPQBn b7A05JYKm8NfF8AnbHbgnRJU/3H9kCMylw/rcYGqXGgs2GDL8qxE1O45vsC0ONJj rKrwRqvz6d8DrSZmEfufI48ykOPKIsWjJw9TKv/8gXNxu0qF9QjqygEKBt4isOZ7 DGqy46RZguhJAESZJkMqydpuLBG+QZ4NKXgm0fi9IhDooj/9qZWLpoaoeSZCO9fC 6ZPGkFA86S9G44bcbrDkp2j86K0lVkoC/Zx/9ZcJMYxauj0/yvDKTH7a/iods7IN xvNxKGgl2en2oADsRAHb3+lGSbdpVo0wMzvf5l8qSMElIJKoDs/L0evykeOQEW83 Kcyd0M3gaX9vSdjrGzrvq6lNXpshGLg/8e+0aAJ9G4x3UKhvc0UnFQ67m1Vmc0Ti WG4WMnD3yXFjiNZjDDrd =f7JV -----END PGP SIGNATURE----- Merge tag 'renesas-r8a7778-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform Pull "Renesas ARM Based SoC r8a7778 CCF and Multiplatform Updates for v4.1" from Simon Horman: * Add CCF and them multiplatform support to r8a7778 SoC and its bockw board. * tag 'renesas-r8a7778-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits) ARM: shmobile: r8a7778: enable multiplatform target ARM: shmobile: bockw: add sound to DT ARM: shmobile: r8a7778: add sound to DT ARM: shmobile: bockw: add devices hooked up to i2c0 to DT DT: i2c: add trivial binding for OKI ML86V7667 video decoder ARM: shmobile: r8a7778: common clock framework CPG driver ARM: shmobile: bockw dts: set extal clock frequency ARM: shmobile: bockw dts: Move Ethernet node to BSC ARM: shmobile: r8a7778 dtsi: Add Bus State Controller node ARM: shmobile: bockw: add USB, VIN pin descriptions to DT ARM: shmobile: r8a7778: add internal ethernet controller to DT ARM: shmobile: r8a7778: add MSTP clock assignments to DT ARM: shmobile: r8a7778: implement SoC and board CCF support ARM: shmobile: r8a7778: Common clock framework DT description ARM: shmobile: r8a7778: add CPG register bits header ARM: shmobile: r8a7778: synchronize dts with reference platform drivers: bus: Add Simple Power-Managed Bus Driver drivers: bus: Add Renesas Bus State Controller (BSC) DT Bindings drivers: bus: Add Simple Power-Managed Bus DT Bindings drivers: bus: Sort Makefile entries alphabetically ...
This commit is contained in:
Arnd Bergmann
commit
369237ab1f
46
Documentation/devicetree/bindings/bus/renesas,bsc.txt
Normal file
46
Documentation/devicetree/bindings/bus/renesas,bsc.txt
Normal file
@ -0,0 +1,46 @@
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Renesas Bus State Controller (BSC)
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==================================
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The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
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Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.
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It provides an external bus for connecting multiple external devices to the
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SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB.
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While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
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domain, and may have a gateable functional clock.
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Before a device connected to the BSC can be accessed, the PM domain
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containing the BSC must be powered on, and the functional clock
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driving the BSC must be enabled.
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The bindings for the BSC extend the bindings for "simple-pm-bus".
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Required properties
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- compatible: Must contain an SoC-specific value, and "renesas,bsc" and
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"simple-pm-bus" as fallbacks.
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SoC-specific values can be:
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"renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)
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"renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)
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- #address-cells, #size-cells, ranges: Must describe the mapping between
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parent address and child address spaces.
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- reg: Must contain the base address and length to access the bus controller.
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Optional properties:
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- interrupts: Must contain a reference to the BSC interrupt, if available.
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- clocks: Must contain a reference to the functional clock, if available.
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- power-domains: Must contain a reference to the PM domain, if available.
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Example:
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bsc: bus@fec10000 {
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compatible = "renesas,bsc-sh73a0", "renesas,bsc",
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"simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x20000000>;
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reg = <0xfec10000 0x400>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&zb_clk>;
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power-domains = <&pd_a4s>;
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};
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44
Documentation/devicetree/bindings/bus/simple-pm-bus.txt
Normal file
44
Documentation/devicetree/bindings/bus/simple-pm-bus.txt
Normal file
@ -0,0 +1,44 @@
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Simple Power-Managed Bus
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========================
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A Simple Power-Managed Bus is a transparent bus that doesn't need a real
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driver, as it's typically initialized by the boot loader.
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However, its bus controller is part of a PM domain, or under the control of a
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functional clock. Hence, the bus controller's PM domain and/or clock must be
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enabled for child devices connected to the bus (either on-SoC or externally)
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to function.
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While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
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in ePAPR, it is not an extension of "simple-bus".
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Required properties:
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- compatible: Must contain at least "simple-pm-bus".
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Must not contain "simple-bus".
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It's recommended to let this be preceded by one or more
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vendor-specific compatible values.
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- #address-cells, #size-cells, ranges: Must describe the mapping between
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parent address and child address spaces.
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Optional platform-specific properties for clock or PM domain control (at least
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one of them is required):
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- clocks: Must contain a reference to the functional clock(s),
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- power-domains: Must contain a reference to the PM domain.
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Please refer to the binding documentation for the clock and/or PM domain
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providers for more details.
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Example:
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bsc: bus@fec10000 {
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compatible = "renesas,bsc-sh73a0", "renesas,bsc",
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"simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x20000000>;
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reg = <0xfec10000 0x400>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&zb_clk>;
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power-domains = <&pd_a4s>;
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};
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@ -0,0 +1,25 @@
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* Renesas R8A7778 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7778. It includes two PLLs and
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several fixed ratio dividers
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Required Properties:
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- compatible: Must be "renesas,r8a7778-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are
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"plla", "pllb", "b", "out", "p", "s", and "s1".
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Example
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-------
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7778-cpg-clocks";
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reg = <0xffc80000 0x80>;
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#clock-cells = <1>;
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clocks = <&extal_clk>;
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clock-output-names = "plla", "pllb", "b",
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"out", "p", "s", "s1";
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};
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@ -77,6 +77,7 @@ nxp,pca9556 Octal SMBus and I2C registered interface
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nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
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nxp,pcf8563 Real-time clock/calendar
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nxp,pcf85063 Tiny Real-Time Clock
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oki,ml86v7667 OKI ML86V7667 video decoder
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ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
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pericom,pt7c4338 Real-time Clock Module
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plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
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@ -477,6 +477,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
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r7s72100-genmai.dtb \
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r8a73a4-ape6evm.dtb \
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r8a7740-armadillo800eva.dtb \
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r8a7778-bockw.dtb \
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r8a7779-marzen.dtb \
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r8a7790-lager.dtb \
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r8a7791-henninger.dtb \
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@ -16,17 +16,191 @@
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/dts-v1/;
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#include "r8a7778.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "bockw";
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compatible = "renesas,bockw", "renesas,r8a7778";
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aliases {
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serial0 = &scif0;
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};
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chosen {
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bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw";
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stdout-path = &scif0;
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};
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memory {
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device_type = "memory";
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reg = <0x60000000 0x10000000>;
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};
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fixedregulator3v3: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "left_j";
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simple-audio-card,bitclock-master = <&sndcodec>;
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simple-audio-card,frame-master = <&sndcodec>;
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sndcpu: simple-audio-card,cpu {
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sound-dai = <&rcar_sound>;
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};
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sndcodec: simple-audio-card,codec {
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sound-dai = <&ak4643>;
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system-clock-frequency = <11289600>;
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};
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};
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};
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&bsc {
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ethernet@18300000 {
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compatible = "smsc,lan9220", "smsc,lan9115";
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reg = <0x18300000 0x1000>;
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phy-mode = "mii";
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interrupt-parent = <&irqpin>;
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interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
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reg-io-width = <4>;
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vddvario-supply = <&fixedregulator3v3>;
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vdd33a-supply = <&fixedregulator3v3>;
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};
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};
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&extal_clk {
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clock-frequency = <33333333>;
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};
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&i2c0 {
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status = "okay";
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ak4643: sound-codec@12 {
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compatible = "asahi-kasei,ak4643";
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#sound-dai-cells = <0>;
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reg = <0x12>;
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};
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camera@41 {
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compatible = "oki,ml86v7667";
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reg = <0x41>;
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};
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camera@43 {
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compatible = "oki,ml86v7667";
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reg = <0x43>;
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};
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rx8581: rtc@51 {
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compatible = "epson,rx8581";
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reg = <0x51>;
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};
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};
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&mmcif {
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pinctrl-0 = <&mmc_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&fixedregulator3v3>;
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bus-width = <8>;
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broken-cd;
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status = "okay";
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};
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&irqpin {
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status = "okay";
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};
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&tmu0 {
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status = "okay";
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};
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&pfc {
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scif0_pins: serial0 {
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renesas,groups = "scif0_data_a", "scif0_ctrl";
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renesas,function = "scif0";
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};
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mmc_pins: mmc {
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renesas,groups = "mmc_data8", "mmc_ctrl";
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renesas,function = "mmc";
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};
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sdhi0_pins: sd0 {
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renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
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"sdhi0_cd";
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renesas,function = "sdhi0";
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};
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hspi0_pins: hspi0 {
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renesas,groups = "hspi0_a";
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renesas,function = "hspi0";
|
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};
|
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usb0_pins: usb0 {
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renesas,groups = "usb0";
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renesas,function = "usb0";
|
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};
|
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|
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usb1_pins: usb1 {
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renesas,groups = "usb1";
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renesas,function = "usb1";
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};
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|
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vin0_pins: vin0 {
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renesas,groups = "vin0_data8", "vin0_clk";
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renesas,function = "vin0";
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};
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|
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vin1_pins: vin1 {
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renesas,groups = "vin1_data8", "vin1_clk";
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renesas,function = "vin1";
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};
|
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};
|
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|
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&sdhi0 {
|
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pinctrl-0 = <&sdhi0_pins>;
|
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pinctrl-names = "default";
|
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|
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vmmc-supply = <&fixedregulator3v3>;
|
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bus-width = <4>;
|
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status = "okay";
|
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wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
|
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};
|
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|
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&hspi0 {
|
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pinctrl-0 = <&hspi0_pins>;
|
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pinctrl-names = "default";
|
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status = "okay";
|
||||
|
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flash: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
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compatible = "spansion,s25fl008k";
|
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reg = <0>;
|
||||
spi-max-frequency = <104000000>;
|
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m25p,fast-read;
|
||||
|
||||
partition@0 {
|
||||
label = "data(spi)";
|
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reg = <0x00000000 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -16,6 +16,7 @@
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
#include <dt-bindings/clock/r8a7778-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
@ -40,6 +41,24 @@
|
||||
spi2 = &hspi2;
|
||||
};
|
||||
|
||||
bsc: bus@1c000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x1c000000>;
|
||||
};
|
||||
|
||||
ether: ethernet@fde00000 {
|
||||
compatible = "renesas,ether-r8a7778";
|
||||
reg = <0xfde00000 0x400>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@fe438000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
@ -132,6 +151,7 @@
|
||||
compatible = "renesas,i2c-r8a7778";
|
||||
reg = <0xffc70000 0x1000>;
|
||||
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -141,6 +161,7 @@
|
||||
compatible = "renesas,i2c-r8a7778";
|
||||
reg = <0xffc71000 0x1000>;
|
||||
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -150,6 +171,7 @@
|
||||
compatible = "renesas,i2c-r8a7778";
|
||||
reg = <0xffc72000 0x1000>;
|
||||
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -159,6 +181,7 @@
|
||||
compatible = "renesas,i2c-r8a7778";
|
||||
reg = <0xffc73000 0x1000>;
|
||||
interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -168,6 +191,8 @@
|
||||
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
|
||||
clock-names = "fck";
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -180,6 +205,8 @@
|
||||
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
|
||||
clock-names = "fck";
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -192,16 +219,75 @@
|
||||
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
|
||||
clock-names = "fck";
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcar_sound: sound@ffd90000 {
|
||||
#sound-dai-cells = <1>;
|
||||
compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
|
||||
reg = <0xffd90000 0x1000>, /* SRU */
|
||||
<0xffd91000 0x1240>, /* SSI */
|
||||
<0xfffe0000 0x24>; /* ADG */
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
|
||||
<&mstp3_clks R8A7778_CLK_SSI7>,
|
||||
<&mstp3_clks R8A7778_CLK_SSI6>,
|
||||
<&mstp3_clks R8A7778_CLK_SSI5>,
|
||||
<&mstp3_clks R8A7778_CLK_SSI4>,
|
||||
<&mstp0_clks R8A7778_CLK_SSI3>,
|
||||
<&mstp0_clks R8A7778_CLK_SSI2>,
|
||||
<&mstp0_clks R8A7778_CLK_SSI1>,
|
||||
<&mstp0_clks R8A7778_CLK_SSI0>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC8>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC7>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC6>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC5>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC4>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC3>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC2>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC1>,
|
||||
<&mstp5_clks R8A7778_CLK_SRU_SRC0>,
|
||||
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
|
||||
<&cpg_clocks R8A7778_CLK_S1>;
|
||||
clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
|
||||
"ssi.3", "ssi.2", "ssi.1", "ssi.0",
|
||||
"src.8", "src.7", "src.6", "src.5", "src.4",
|
||||
"src.3", "src.2", "src.1", "src.0",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
rcar_sound,src {
|
||||
src3: src@3 { };
|
||||
src4: src@4 { };
|
||||
src5: src@5 { };
|
||||
src6: src@6 { };
|
||||
src7: src@7 { };
|
||||
src8: src@8 { };
|
||||
src9: src@9 { };
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
};
|
||||
};
|
||||
|
||||
scif0: serial@ffe40000 {
|
||||
compatible = "renesas,scif-r8a7778", "renesas,scif";
|
||||
reg = <0xffe40000 0x100>;
|
||||
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
|
||||
clock-names = "sci_ick";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -209,6 +295,8 @@
|
||||
compatible = "renesas,scif-r8a7778", "renesas,scif";
|
||||
reg = <0xffe41000 0x100>;
|
||||
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
|
||||
clock-names = "sci_ick";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -216,6 +304,8 @@
|
||||
compatible = "renesas,scif-r8a7778", "renesas,scif";
|
||||
reg = <0xffe42000 0x100>;
|
||||
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
|
||||
clock-names = "sci_ick";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -223,6 +313,8 @@
|
||||
compatible = "renesas,scif-r8a7778", "renesas,scif";
|
||||
reg = <0xffe43000 0x100>;
|
||||
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
|
||||
clock-names = "sci_ick";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -230,6 +322,8 @@
|
||||
compatible = "renesas,scif-r8a7778", "renesas,scif";
|
||||
reg = <0xffe44000 0x100>;
|
||||
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
|
||||
clock-names = "sci_ick";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -237,6 +331,8 @@
|
||||
compatible = "renesas,scif-r8a7778", "renesas,scif";
|
||||
reg = <0xffe45000 0x100>;
|
||||
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
|
||||
clock-names = "sci_ick";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -244,6 +340,7 @@
|
||||
compatible = "renesas,sh-mmcif";
|
||||
reg = <0xffe4e000 0x100>;
|
||||
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_MMC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -251,6 +348,7 @@
|
||||
compatible = "renesas,sdhi-r8a7778";
|
||||
reg = <0xffe4c000 0x100>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -258,6 +356,7 @@
|
||||
compatible = "renesas,sdhi-r8a7778";
|
||||
reg = <0xffe4d000 0x100>;
|
||||
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -265,6 +364,7 @@
|
||||
compatible = "renesas,sdhi-r8a7778";
|
||||
reg = <0xffe4f000 0x100>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -272,6 +372,7 @@
|
||||
compatible = "renesas,hspi-r8a7778", "renesas,hspi";
|
||||
reg = <0xfffc7000 0x18>;
|
||||
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -281,6 +382,7 @@
|
||||
compatible = "renesas,hspi-r8a7778", "renesas,hspi";
|
||||
reg = <0xfffc8000 0x18>;
|
||||
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -290,8 +392,199 @@
|
||||
compatible = "renesas,hspi-r8a7778", "renesas,hspi";
|
||||
reg = <0xfffc6000 0x18>;
|
||||
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* External input clock */
|
||||
extal_clk: extal_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7778-cpg-clocks";
|
||||
reg = <0xffc80000 0x80>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-output-names = "plla", "pllb", "b",
|
||||
"out", "p", "s", "s1";
|
||||
};
|
||||
|
||||
/* Audio clocks; frequencies are set by boards if applicable. */
|
||||
audio_clk_a: audio_clk_a {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "audio_clk_a";
|
||||
};
|
||||
audio_clk_b: audio_clk_b {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "audio_clk_b";
|
||||
};
|
||||
audio_clk_c: audio_clk_c {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "audio_clk_c";
|
||||
};
|
||||
|
||||
/* Fixed ratio clocks */
|
||||
g_clk: g_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "g";
|
||||
};
|
||||
i_clk: i_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "i";
|
||||
};
|
||||
s3_clk: s3_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "s3";
|
||||
};
|
||||
s4_clk: s4_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "s4";
|
||||
};
|
||||
z_clk: z_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "z";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
mstp0_clks: mstp0_clks@ffc80030 {
|
||||
compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xffc80030 4>;
|
||||
clocks = <&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_S>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
|
||||
R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
|
||||
R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
|
||||
R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
|
||||
R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
|
||||
R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
|
||||
R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
|
||||
R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
|
||||
R8A7778_CLK_SSI3 R8A7778_CLK_SRU
|
||||
R8A7778_CLK_HSPI
|
||||
>;
|
||||
clock-output-names =
|
||||
"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
|
||||
"scif1", "scif2", "scif3", "scif4", "scif5",
|
||||
"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
|
||||
"ssi2", "ssi3", "sru", "hspi";
|
||||
};
|
||||
mstp1_clks: mstp1_clks@ffc80034 {
|
||||
compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xffc80034 4>, <0xffc80044 4>;
|
||||
clocks = <&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_S>,
|
||||
<&cpg_clocks R8A7778_CLK_S>,
|
||||
<&cpg_clocks R8A7778_CLK_P>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7778_CLK_ETHER R8A7778_CLK_VIN0
|
||||
R8A7778_CLK_VIN1 R8A7778_CLK_USB
|
||||
>;
|
||||
clock-output-names =
|
||||
"ether", "vin0", "vin1", "usb";
|
||||
};
|
||||
mstp3_clks: mstp3_clks@ffc8003c {
|
||||
compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xffc8003c 4>;
|
||||
clocks = <&s4_clk>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7778_CLK_MMC R8A7778_CLK_SDHI0
|
||||
R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
|
||||
R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
|
||||
R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
|
||||
R8A7778_CLK_SSI8
|
||||
>;
|
||||
clock-output-names =
|
||||
"mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
|
||||
"ssi5", "ssi6", "ssi7", "ssi8";
|
||||
};
|
||||
mstp5_clks: mstp5_clks@ffc80054 {
|
||||
compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xffc80054 4>;
|
||||
clocks = <&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>,
|
||||
<&cpg_clocks R8A7778_CLK_P>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
|
||||
R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
|
||||
R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
|
||||
R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
|
||||
R8A7778_CLK_SRU_SRC8
|
||||
>;
|
||||
clock-output-names =
|
||||
"sru-src0", "sru-src1", "sru-src2",
|
||||
"sru-src3", "sru-src4", "sru-src5",
|
||||
"sru-src6", "sru-src7", "sru-src8";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -62,6 +62,10 @@ config ARCH_R8A7740
|
||||
select ARCH_RMOBILE
|
||||
select RENESAS_INTC_IRQPIN
|
||||
|
||||
config ARCH_R8A7778
|
||||
bool "R-Car M1A (R8A77781)"
|
||||
select ARCH_RCAR_GEN1
|
||||
|
||||
config ARCH_R8A7779
|
||||
bool "R-Car H1 (R8A77790)"
|
||||
select ARCH_RCAR_GEN1
|
||||
|
||||
@ -36,7 +36,9 @@ static void __init bockw_init(void)
|
||||
void __iomem *fpga;
|
||||
void __iomem *pfc;
|
||||
|
||||
#ifndef CONFIG_COMMON_CLK
|
||||
r8a7778_clock_init();
|
||||
#endif
|
||||
r8a7778_init_irq_extpin_dt(1);
|
||||
r8a7778_add_dt_devices();
|
||||
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk/shmobile.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
@ -41,6 +42,21 @@
|
||||
#include "irqs.h"
|
||||
#include "r8a7778.h"
|
||||
|
||||
#define MODEMR 0xffcc0020
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
static void __init r8a7778_timer_init(void)
|
||||
{
|
||||
u32 mode;
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
r8a7778_clocks_init(mode);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* SCIF */
|
||||
#define R8A7778_SCIF(index, baseaddr, irq) \
|
||||
static struct plat_sci_port scif##index##_platform_data = { \
|
||||
@ -608,6 +624,9 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
|
||||
.init_early = shmobile_init_delay,
|
||||
.init_irq = r8a7778_init_irq_dt,
|
||||
.init_late = shmobile_init_late,
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
.init_time = r8a7778_timer_init,
|
||||
#endif
|
||||
.dt_compat = r8a7778_compat_dt,
|
||||
MACHINE_END
|
||||
|
||||
|
||||
@ -4,6 +4,21 @@
|
||||
|
||||
menu "Bus devices"
|
||||
|
||||
config ARM_CCI
|
||||
bool "ARM CCI driver support"
|
||||
depends on ARM && OF && CPU_V7
|
||||
help
|
||||
Driver supporting the CCI cache coherent interconnect for ARM
|
||||
platforms.
|
||||
|
||||
config ARM_CCN
|
||||
bool "ARM CCN driver support"
|
||||
depends on ARM || ARM64
|
||||
depends on PERF_EVENTS
|
||||
help
|
||||
PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
|
||||
interconnect.
|
||||
|
||||
config BRCMSTB_GISB_ARB
|
||||
bool "Broadcom STB GISB bus arbiter"
|
||||
depends on ARM || MIPS
|
||||
@ -27,6 +42,13 @@ config MVEBU_MBUS
|
||||
Driver needed for the MBus configuration on Marvell EBU SoCs
|
||||
(Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
|
||||
|
||||
config OMAP_INTERCONNECT
|
||||
tristate "OMAP INTERCONNECT DRIVER"
|
||||
depends on ARCH_OMAP2PLUS
|
||||
|
||||
help
|
||||
Driver to enable OMAP interconnect error handling driver.
|
||||
|
||||
config OMAP_OCP2SCP
|
||||
tristate "OMAP OCP2SCP DRIVER"
|
||||
depends on ARCH_OMAP2PLUS
|
||||
@ -36,27 +58,18 @@ config OMAP_OCP2SCP
|
||||
OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
|
||||
OCP2SCP.
|
||||
|
||||
config OMAP_INTERCONNECT
|
||||
tristate "OMAP INTERCONNECT DRIVER"
|
||||
depends on ARCH_OMAP2PLUS
|
||||
|
||||
config SIMPLE_PM_BUS
|
||||
bool "Simple Power-Managed Bus Driver"
|
||||
depends on OF && PM
|
||||
depends on ARCH_SHMOBILE || COMPILE_TEST
|
||||
help
|
||||
Driver to enable OMAP interconnect error handling driver.
|
||||
|
||||
config ARM_CCI
|
||||
bool "ARM CCI driver support"
|
||||
depends on ARM && OF && CPU_V7
|
||||
help
|
||||
Driver supporting the CCI cache coherent interconnect for ARM
|
||||
platforms.
|
||||
|
||||
config ARM_CCN
|
||||
bool "ARM CCN driver support"
|
||||
depends on ARM || ARM64
|
||||
depends on PERF_EVENTS
|
||||
help
|
||||
PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
|
||||
interconnect.
|
||||
Driver for transparent busses that don't need a real driver, but
|
||||
where the bus controller is part of a PM domain, or under the control
|
||||
of a functional clock, and thus relies on runtime PM for managing
|
||||
this PM domain and/or clock.
|
||||
An example of such a bus controller is the Renesas Bus State
|
||||
Controller (BSC, sometimes called "LBSC within Bus Bridge", or
|
||||
"External Bus Interface") as found on several Renesas ARM SoCs.
|
||||
|
||||
config VEXPRESS_CONFIG
|
||||
bool "Versatile Express configuration bus"
|
||||
|
||||
@ -2,16 +2,17 @@
|
||||
# Makefile for the bus drivers.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
|
||||
obj-$(CONFIG_IMX_WEIM) += imx-weim.o
|
||||
obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
|
||||
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
|
||||
|
||||
# Interconnect bus driver for OMAP SoCs.
|
||||
obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
|
||||
|
||||
# Interconnect bus drivers for ARM platforms
|
||||
obj-$(CONFIG_ARM_CCI) += arm-cci.o
|
||||
obj-$(CONFIG_ARM_CCN) += arm-ccn.o
|
||||
|
||||
obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
|
||||
obj-$(CONFIG_IMX_WEIM) += imx-weim.o
|
||||
obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
|
||||
|
||||
# Interconnect bus driver for OMAP SoCs.
|
||||
obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
|
||||
|
||||
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
|
||||
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
|
||||
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
|
||||
|
||||
58
drivers/bus/simple-pm-bus.c
Normal file
58
drivers/bus/simple-pm-bus.c
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Simple Power-Managed Bus Driver
|
||||
*
|
||||
* Copyright (C) 2014-2015 Glider bvba
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
|
||||
static int simple_pm_bus_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
|
||||
dev_dbg(&pdev->dev, "%s\n", __func__);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
if (np)
|
||||
of_platform_populate(np, NULL, NULL, &pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int simple_pm_bus_remove(struct platform_device *pdev)
|
||||
{
|
||||
dev_dbg(&pdev->dev, "%s\n", __func__);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id simple_pm_bus_of_match[] = {
|
||||
{ .compatible = "simple-pm-bus", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, simple_pm_bus_of_match);
|
||||
|
||||
static struct platform_driver simple_pm_bus_driver = {
|
||||
.probe = simple_pm_bus_probe,
|
||||
.remove = simple_pm_bus_remove,
|
||||
.driver = {
|
||||
.name = "simple-pm-bus",
|
||||
.of_match_table = simple_pm_bus_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(simple_pm_bus_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Simple Power-Managed Bus Driver");
|
||||
MODULE_AUTHOR("Geert Uytterhoeven <geert+renesas@glider.be>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
|
||||
obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
|
||||
obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
|
||||
obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
|
||||
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
|
||||
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
|
||||
|
||||
143
drivers/clk/shmobile/clk-r8a7778.c
Normal file
143
drivers/clk/shmobile/clk-r8a7778.c
Normal file
@ -0,0 +1,143 @@
|
||||
/*
|
||||
* r8a7778 Core CPG Clocks
|
||||
*
|
||||
* Copyright (C) 2014 Ulrich Hecht
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk/shmobile.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
struct r8a7778_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
|
||||
struct {
|
||||
unsigned long plla_mult;
|
||||
unsigned long pllb_mult;
|
||||
} r8a7778_rates[] __initdata = {
|
||||
[0] = { 21, 21 },
|
||||
[1] = { 24, 24 },
|
||||
[2] = { 28, 28 },
|
||||
[3] = { 32, 32 },
|
||||
[5] = { 24, 21 },
|
||||
[6] = { 28, 21 },
|
||||
[7] = { 32, 24 },
|
||||
};
|
||||
|
||||
/* Clock dividers per bits 1 and 2 of MODEMR */
|
||||
struct {
|
||||
const char *name;
|
||||
unsigned int div[4];
|
||||
} r8a7778_divs[6] __initdata = {
|
||||
{ "b", { 12, 12, 16, 18 } },
|
||||
{ "out", { 12, 12, 16, 18 } },
|
||||
{ "p", { 16, 12, 16, 12 } },
|
||||
{ "s", { 4, 3, 4, 3 } },
|
||||
{ "s1", { 8, 6, 8, 6 } },
|
||||
};
|
||||
|
||||
static u32 cpg_mode_rates __initdata;
|
||||
static u32 cpg_mode_divs __initdata;
|
||||
|
||||
static struct clk * __init
|
||||
r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
|
||||
const char *name)
|
||||
{
|
||||
if (!strcmp(name, "plla")) {
|
||||
return clk_register_fixed_factor(NULL, "plla",
|
||||
of_clk_get_parent_name(np, 0), 0,
|
||||
r8a7778_rates[cpg_mode_rates].plla_mult, 1);
|
||||
} else if (!strcmp(name, "pllb")) {
|
||||
return clk_register_fixed_factor(NULL, "pllb",
|
||||
of_clk_get_parent_name(np, 0), 0,
|
||||
r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
|
||||
} else {
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
|
||||
if (!strcmp(name, r8a7778_divs[i].name)) {
|
||||
return clk_register_fixed_factor(NULL,
|
||||
r8a7778_divs[i].name,
|
||||
"plla", 0, 1,
|
||||
r8a7778_divs[i].div[cpg_mode_divs]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
|
||||
static void __init r8a7778_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct r8a7778_cpg *cpg;
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
int num_clks;
|
||||
|
||||
num_clks = of_property_count_strings(np, "clock-output-names");
|
||||
if (num_clks < 0) {
|
||||
pr_err("%s: failed to count clocks\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
|
||||
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
|
||||
if (cpg == NULL || clks == NULL) {
|
||||
/* We're leaking memory on purpose, there's no point in cleaning
|
||||
* up as the system won't boot anyway.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_init(&cpg->lock);
|
||||
|
||||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(cpg->reg == NULL))
|
||||
return;
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
const char *name;
|
||||
struct clk *clk;
|
||||
|
||||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = r8a7778_cpg_register_clock(np, cpg, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %s %s clock (%ld)\n",
|
||||
__func__, np->name, name, PTR_ERR(clk));
|
||||
else
|
||||
cpg->data.clks[i] = clk;
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
|
||||
r8a7778_cpg_clocks_init);
|
||||
|
||||
void __init r8a7778_clocks_init(u32 mode)
|
||||
{
|
||||
BUG_ON(!(mode & BIT(19)));
|
||||
|
||||
cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
|
||||
(!!(mode & BIT(12)) << 1) |
|
||||
(!!(mode & BIT(11)));
|
||||
cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
|
||||
(!!(mode & BIT(1)));
|
||||
|
||||
of_clk_init(NULL);
|
||||
}
|
||||
71
include/dt-bindings/clock/r8a7778-clock.h
Normal file
71
include/dt-bindings/clock/r8a7778-clock.h
Normal file
@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Ulrich Hecht
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7778_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7778_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7778_CLK_PLLA 0
|
||||
#define R8A7778_CLK_PLLB 1
|
||||
#define R8A7778_CLK_B 2
|
||||
#define R8A7778_CLK_OUT 3
|
||||
#define R8A7778_CLK_P 4
|
||||
#define R8A7778_CLK_S 5
|
||||
#define R8A7778_CLK_S1 6
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7778_CLK_I2C0 30
|
||||
#define R8A7778_CLK_I2C1 29
|
||||
#define R8A7778_CLK_I2C2 28
|
||||
#define R8A7778_CLK_I2C3 27
|
||||
#define R8A7778_CLK_SCIF0 26
|
||||
#define R8A7778_CLK_SCIF1 25
|
||||
#define R8A7778_CLK_SCIF2 24
|
||||
#define R8A7778_CLK_SCIF3 23
|
||||
#define R8A7778_CLK_SCIF4 22
|
||||
#define R8A7778_CLK_SCIF5 21
|
||||
#define R8A7778_CLK_TMU0 16
|
||||
#define R8A7778_CLK_TMU1 15
|
||||
#define R8A7778_CLK_TMU2 14
|
||||
#define R8A7778_CLK_SSI0 12
|
||||
#define R8A7778_CLK_SSI1 11
|
||||
#define R8A7778_CLK_SSI2 10
|
||||
#define R8A7778_CLK_SSI3 9
|
||||
#define R8A7778_CLK_SRU 8
|
||||
#define R8A7778_CLK_HSPI 7
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7778_CLK_ETHER 14
|
||||
#define R8A7778_CLK_VIN0 10
|
||||
#define R8A7778_CLK_VIN1 9
|
||||
#define R8A7778_CLK_USB 0
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7778_CLK_MMC 31
|
||||
#define R8A7778_CLK_SDHI0 23
|
||||
#define R8A7778_CLK_SDHI1 22
|
||||
#define R8A7778_CLK_SDHI2 21
|
||||
#define R8A7778_CLK_SSI4 11
|
||||
#define R8A7778_CLK_SSI5 10
|
||||
#define R8A7778_CLK_SSI6 9
|
||||
#define R8A7778_CLK_SSI7 8
|
||||
#define R8A7778_CLK_SSI8 7
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7778_CLK_SRU_SRC0 31
|
||||
#define R8A7778_CLK_SRU_SRC1 30
|
||||
#define R8A7778_CLK_SRU_SRC2 29
|
||||
#define R8A7778_CLK_SRU_SRC3 28
|
||||
#define R8A7778_CLK_SRU_SRC4 27
|
||||
#define R8A7778_CLK_SRU_SRC5 26
|
||||
#define R8A7778_CLK_SRU_SRC6 25
|
||||
#define R8A7778_CLK_SRU_SRC7 24
|
||||
#define R8A7778_CLK_SRU_SRC8 23
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */
|
||||
@ -16,6 +16,7 @@
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
void r8a7778_clocks_init(u32 mode);
|
||||
void r8a7779_clocks_init(u32 mode);
|
||||
void rcar_gen2_clocks_init(u32 mode);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user