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ARM: tegra: cleanup use of chipid register

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The chipid register contains information about the Tegra variant and revision.
We want differentiate between Tegra variants for powergating and secondary
core bringup. This patch cleans up the reading and decoding of this register.
In subsequent patches the variant will exported as a global variable.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Peter De Schrijver 2012-02-10 01:47:41 +02:00 committed by Olof Johansson
parent 0f830e5c90
commit 35b1498a34
2 changed files with 14 additions and 7 deletions
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18
arch/arm/mach-tegra/fuse.c
View File

@ -33,6 +33,7 @@
int tegra_sku_id; int tegra_sku_id;
int tegra_cpu_process_id; int tegra_cpu_process_id;
int tegra_core_process_id; int tegra_core_process_id;
static int tegra_chip_id;
enum tegra_revision tegra_revision; enum tegra_revision tegra_revision;
/* The BCT to use at boot is specified by board straps that can be read /* The BCT to use at boot is specified by board straps that can be read
@ -65,12 +66,9 @@ static inline bool get_spare_fuse(int bit)
return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
} }
static enum tegra_revision tegra_get_revision(void) static enum tegra_revision tegra_get_revision(u32 id)
{ {
void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
u32 id = readl(chip_id);
u32 minor_rev = (id >> 16) & 0xf; u32 minor_rev = (id >> 16) & 0xf;
u32 chipid = (id >> 8) & 0xff;
switch (minor_rev) { switch (minor_rev) {
case 1: case 1:
@ -78,7 +76,8 @@ static enum tegra_revision tegra_get_revision(void)
case 2: case 2:
return TEGRA_REVISION_A02; return TEGRA_REVISION_A02;
case 3: case 3:
if (chipid == 0x20 && (get_spare_fuse(18) || get_spare_fuse(19))) if (tegra_chip_id == TEGRA20 &&
(get_spare_fuse(18) || get_spare_fuse(19)))
return TEGRA_REVISION_A03p; return TEGRA_REVISION_A03p;
else else
return TEGRA_REVISION_A03; return TEGRA_REVISION_A03;
@ -91,6 +90,8 @@ static enum tegra_revision tegra_get_revision(void)
void tegra_init_fuse(void) void tegra_init_fuse(void)
{ {
u32 id;
u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
reg |= 1 << 28; reg |= 1 << 28;
writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
@ -107,10 +108,13 @@ void tegra_init_fuse(void)
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
tegra_revision = tegra_get_revision(); id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
tegra_chip_id = (id >> 8) & 0xff;
tegra_revision = tegra_get_revision(id);
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
tegra_revision_name[tegra_get_revision()], tegra_revision_name[tegra_revision],
tegra_sku_id, tegra_cpu_process_id, tegra_sku_id, tegra_cpu_process_id,
tegra_core_process_id); tegra_core_process_id);
} }

3
arch/arm/mach-tegra/fuse.h
View File

@ -35,6 +35,9 @@ enum tegra_revision {
#define SKU_ID_AP25E 27 #define SKU_ID_AP25E 27
#define SKU_ID_T25E 28 #define SKU_ID_T25E 28
#define TEGRA20 0x20
#define TEGRA30 0x30
extern int tegra_sku_id; extern int tegra_sku_id;
extern int tegra_cpu_process_id; extern int tegra_cpu_process_id;
extern int tegra_core_process_id; extern int tegra_core_process_id;