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[MIPS] Support for the RM9000-based Basler eXcite smart camera platform.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
355c471f2f
commit
35189fad3c
@ -119,6 +119,32 @@ config MIPS_MIRAGE
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_LITTLE_ENDIAN
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config BASLER_EXCITE
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bool "Basler eXcite smart camera support"
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select DMA_COHERENT
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select HW_HAS_PCI
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select IRQ_CPU
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select IRQ_CPU_RM7K
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select IRQ_CPU_RM9K
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select SERIAL_RM9000
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select SYS_HAS_CPU_RM9000
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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help
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The eXcite is a smart camera platform manufactured by
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Basler Vision Technologies AG
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config BASLER_EXCITE_PROTOTYPE
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bool "Support for pre-release units"
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depends on BASLER_EXCITE
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default n
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help
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Pre-series (prototype) units are different from later ones in
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some ways. Select this option if you have one of these. Please
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note that a kernel built with this option selected will not be
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able to run on normal units.
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config MIPS_COBALT
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bool "Cobalt Server"
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select DMA_NONCOHERENT
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@ -387,6 +387,13 @@ core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/
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cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3
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load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000
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#
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# Basler eXcite
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#
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core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
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cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
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load-$(CONFIG_BASLER_EXCITE) += 0x80100000
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#
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# Momentum Jaguar ATX
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#
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9
arch/mips/basler/excite/Makefile
Normal file
9
arch/mips/basler/excite/Makefile
Normal file
@ -0,0 +1,9 @@
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#
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# Makefile for Basler eXcite
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#
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obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
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excite_device.o excite_procfs.o
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obj-$(CONFIG_KGDB) += excite_dbg_io.o
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obj-m += excite_iodev.o
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122
arch/mips/basler/excite/excite_dbg_io.c
Normal file
122
arch/mips/basler/excite/excite_dbg_io.c
Normal file
@ -0,0 +1,122 @@
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/*
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* Copyright (C) 2004 by Basler Vision Technologies AG
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* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/gdb-stub.h>
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#include <asm/rm9k-ocd.h>
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#include <excite.h>
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#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
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#error Debug port used by serial driver
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#endif
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#define UART_CLK 25000000
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#define BASE_BAUD (UART_CLK / 16)
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#define REGISTER_BASE_0 0x0208UL
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#define REGISTER_BASE_1 0x0238UL
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#define REGISTER_BASE_DBG REGISTER_BASE_1
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#define CPRR 0x0004
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#define UACFG 0x0200
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#define UAINTS 0x0204
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#define UARBR (REGISTER_BASE_DBG + 0x0000)
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#define UATHR (REGISTER_BASE_DBG + 0x0004)
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#define UADLL (REGISTER_BASE_DBG + 0x0008)
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#define UAIER (REGISTER_BASE_DBG + 0x000c)
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#define UADLH (REGISTER_BASE_DBG + 0x0010)
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#define UAIIR (REGISTER_BASE_DBG + 0x0014)
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#define UAFCR (REGISTER_BASE_DBG + 0x0018)
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#define UALCR (REGISTER_BASE_DBG + 0x001c)
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#define UAMCR (REGISTER_BASE_DBG + 0x0020)
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#define UALSR (REGISTER_BASE_DBG + 0x0024)
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#define UAMSR (REGISTER_BASE_DBG + 0x0028)
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#define UASCR (REGISTER_BASE_DBG + 0x002c)
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#define PARITY_NONE 0
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#define PARITY_ODD 0x08
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#define PARITY_EVEN 0x18
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#define PARITY_MARK 0x28
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#define PARITY_SPACE 0x38
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#define DATA_5BIT 0x0
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#define DATA_6BIT 0x1
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#define DATA_7BIT 0x2
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#define DATA_8BIT 0x3
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#define STOP_1BIT 0x0
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#define STOP_2BIT 0x4
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#define BAUD_DBG 57600
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#define PARITY_DBG PARITY_NONE
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#define DATA_DBG DATA_8BIT
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#define STOP_DBG STOP_1BIT
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/* Initialize the serial port for KGDB debugging */
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void __init excite_kgdb_init(void)
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{
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const u32 divisor = BASE_BAUD / BAUD_DBG;
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/* Take the UART out of reset */
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titan_writel(0x00ff1cff, CPRR);
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titan_writel(0x00000000, UACFG);
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titan_writel(0x00000002, UACFG);
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titan_writel(0x0, UALCR);
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titan_writel(0x0, UAIER);
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/* Disable FIFOs */
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titan_writel(0x00, UAFCR);
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titan_writel(0x80, UALCR);
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titan_writel(divisor & 0xff, UADLL);
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titan_writel((divisor & 0xff00) >> 8, UADLH);
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titan_writel(0x0, UALCR);
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titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
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/* Enable receiver interrupt */
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titan_readl(UARBR);
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titan_writel(0x1, UAIER);
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}
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int getDebugChar(void)
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{
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while (!(titan_readl(UALSR) & 0x1));
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return titan_readl(UARBR);
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}
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int putDebugChar(int data)
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{
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while (!(titan_readl(UALSR) & 0x20));
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titan_writel(data, UATHR);
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return 1;
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}
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/* KGDB interrupt handler */
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asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
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{
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if (unlikely(
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((titan_readl(UAIIR) & 0x7) == 4)
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&& ((titan_readl(UARBR) & 0xff) == 0x3)))
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set_async_breakpoint(®s->cp0_epc);
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}
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404
arch/mips/basler/excite/excite_device.c
Normal file
404
arch/mips/basler/excite/excite_device.c
Normal file
@ -0,0 +1,404 @@
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/*
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* Copyright (C) 2004 by Basler Vision Technologies AG
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* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/ioport.h>
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#include <linux/err.h>
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#include <linux/jiffies.h>
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#include <linux/sched.h>
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#include <asm/types.h>
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#include <asm/rm9k-ocd.h>
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#include <excite.h>
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#include <rm9k_eth.h>
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#include <rm9k_wdt.h>
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#include <rm9k_xicap.h>
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#include <excite_nandflash.h>
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#include "excite_iodev.h"
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#define RM9K_GE_UNIT 0
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#define XICAP_UNIT 0
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#define NAND_UNIT 0
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#define DLL_TIMEOUT 3 /* seconds */
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#define RINIT(__start__, __end__, __name__, __parent__) { \
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.name = __name__ "_0", \
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.start = (__start__), \
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.end = (__end__), \
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.flags = 0, \
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.parent = (__parent__) \
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}
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#define RINIT_IRQ(__irq__, __name__) { \
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.name = __name__ "_0", \
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.start = (__irq__), \
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.end = (__irq__), \
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.flags = IORESOURCE_IRQ, \
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.parent = NULL \
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}
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enum {
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slice_xicap,
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slice_eth
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};
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static struct resource
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excite_ctr_resource = {
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.name = "GPI counters",
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.start = 0,
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.end = 5,
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.flags = 0,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_gpislice_resource = {
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.name = "GPI slices",
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.start = 0,
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.end = 1,
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.flags = 0,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_mdio_channel_resource = {
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.name = "MDIO channels",
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.start = 0,
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.end = 1,
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.flags = 0,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_fifomem_resource = {
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.name = "FIFO memory",
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.start = 0,
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.end = 767,
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.flags = 0,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_scram_resource = {
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.name = "Scratch RAM",
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.start = EXCITE_PHYS_SCRAM,
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.end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
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.flags = IORESOURCE_MEM,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_fpga_resource = {
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.name = "System FPGA",
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.start = EXCITE_PHYS_FPGA,
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.end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
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.flags = IORESOURCE_MEM,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_nand_resource = {
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.name = "NAND flash control",
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.start = EXCITE_PHYS_NAND,
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.end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
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.flags = IORESOURCE_MEM,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_titan_resource = {
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.name = "TITAN registers",
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.start = EXCITE_PHYS_TITAN,
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.end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
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.flags = IORESOURCE_MEM,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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};
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static void adjust_resources(struct resource *res, unsigned int n)
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{
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struct resource *p;
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const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
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| IORESOURCE_IRQ | IORESOURCE_DMA;
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for (p = res; p < res + n; p++) {
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const struct resource * const parent = p->parent;
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if (parent) {
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p->start += parent->start;
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p->end += parent->start;
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p->flags = parent->flags & mask;
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}
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}
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}
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#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
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static struct resource xicap_rsrc[] = {
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RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
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RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
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RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
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RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
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RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
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RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
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RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
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RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
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RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
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};
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static struct platform_device xicap_pdev = {
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.name = XICAP_NAME,
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.id = XICAP_UNIT,
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.num_resources = ARRAY_SIZE(xicap_rsrc),
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.resource = xicap_rsrc
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};
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/*
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* Create a platform device for the GPI port that receives the
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* image data from the embedded camera.
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*/
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static int __init xicap_devinit(void)
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{
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unsigned long tend;
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u32 reg;
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int retval;
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adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
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/* Power up the slice and configure it. */
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reg = titan_readl(CPTC1R);
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reg &= ~(0x11100 << slice_xicap);
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titan_writel(reg, CPTC1R);
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/* Enable slice & DLL. */
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reg= titan_readl(CPRR);
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reg &= ~(0x00030003 << (slice_xicap * 2));
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titan_writel(reg, CPRR);
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/* Wait for DLLs to lock */
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tend = jiffies + DLL_TIMEOUT * HZ;
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while (time_before(jiffies, tend)) {
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if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
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break;
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yield();
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}
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if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
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printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
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xicap_pdev.name, DLL_TIMEOUT);
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retval = -ETIME;
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} else {
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/* Register platform device */
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retval = platform_device_register(&xicap_pdev);
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}
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return retval;
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}
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device_initcall(xicap_devinit);
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#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
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#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
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static struct resource wdt_rsrc[] = {
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RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
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RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
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RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
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};
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static struct platform_device wdt_pdev = {
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.name = WDT_NAME,
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.id = -1,
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.num_resources = ARRAY_SIZE(wdt_rsrc),
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.resource = wdt_rsrc
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};
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/*
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* Create a platform device for the GPI port that receives the
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* image data from the embedded camera.
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*/
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static int __init wdt_devinit(void)
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{
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adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
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return platform_device_register(&wdt_pdev);
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}
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device_initcall(wdt_devinit);
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#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
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static struct resource excite_nandflash_rsrc[] = {
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RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
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||||
};
|
||||
|
||||
static struct platform_device excite_nandflash_pdev = {
|
||||
.name = "excite_nand",
|
||||
.id = NAND_UNIT,
|
||||
.num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
|
||||
.resource = excite_nandflash_rsrc
|
||||
};
|
||||
|
||||
/*
|
||||
* Create a platform device for the access to the nand-flash
|
||||
* port
|
||||
*/
|
||||
static int __init excite_nandflash_devinit(void)
|
||||
{
|
||||
adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
|
||||
|
||||
/* nothing to be done here */
|
||||
|
||||
/* Register platform device */
|
||||
return platform_device_register(&excite_nandflash_pdev);
|
||||
}
|
||||
|
||||
device_initcall(excite_nandflash_devinit);
|
||||
|
||||
|
||||
|
||||
static struct resource iodev_rsrc[] = {
|
||||
RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
|
||||
};
|
||||
|
||||
static struct platform_device io_pdev = {
|
||||
.name = IODEV_NAME,
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(iodev_rsrc),
|
||||
.resource = iodev_rsrc
|
||||
};
|
||||
|
||||
/*
|
||||
* Create a platform device for the external I/O ports.
|
||||
*/
|
||||
static int __init io_devinit(void)
|
||||
{
|
||||
adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
|
||||
return platform_device_register(&io_pdev);
|
||||
}
|
||||
|
||||
device_initcall(io_devinit);
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
|
||||
static struct resource rm9k_ge_rsrc[] = {
|
||||
RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
|
||||
RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
|
||||
RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
|
||||
RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
|
||||
RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
|
||||
RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
|
||||
RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
|
||||
RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
|
||||
RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
|
||||
RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
|
||||
RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
|
||||
RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
|
||||
RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
|
||||
RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
|
||||
RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
|
||||
};
|
||||
|
||||
static struct platform_device rm9k_ge_pdev = {
|
||||
.name = RM9K_GE_NAME,
|
||||
.id = RM9K_GE_UNIT,
|
||||
.num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
|
||||
.resource = rm9k_ge_rsrc
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Create a platform device for the Ethernet port.
|
||||
*/
|
||||
static int __init rm9k_ge_devinit(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
|
||||
|
||||
/* Power up the slice and configure it. */
|
||||
reg = titan_readl(CPTC1R);
|
||||
reg &= ~(0x11000 << slice_eth);
|
||||
reg |= 0x100 << slice_eth;
|
||||
titan_writel(reg, CPTC1R);
|
||||
|
||||
/* Take the MAC out of reset, reset the DLLs. */
|
||||
reg = titan_readl(CPRR);
|
||||
reg &= ~(0x00030000 << (slice_eth * 2));
|
||||
reg |= 0x3 << (slice_eth * 2);
|
||||
titan_writel(reg, CPRR);
|
||||
|
||||
return platform_device_register(&rm9k_ge_pdev);
|
||||
}
|
||||
|
||||
device_initcall(rm9k_ge_devinit);
|
||||
#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
|
||||
|
||||
|
||||
|
||||
static int __init excite_setup_devs(void)
|
||||
{
|
||||
int res;
|
||||
u32 reg;
|
||||
|
||||
/* Enable xdma and fifo interrupts */
|
||||
reg = titan_readl(0x0050);
|
||||
titan_writel(reg | 0x18000000, 0x0050);
|
||||
|
||||
res = request_resource(&iomem_resource, &excite_titan_resource);
|
||||
if (res)
|
||||
return res;
|
||||
res = request_resource(&iomem_resource, &excite_scram_resource);
|
||||
if (res)
|
||||
return res;
|
||||
res = request_resource(&iomem_resource, &excite_fpga_resource);
|
||||
if (res)
|
||||
return res;
|
||||
res = request_resource(&iomem_resource, &excite_nand_resource);
|
||||
if (res)
|
||||
return res;
|
||||
excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
|
||||
( IORESOURCE_IO | IORESOURCE_MEM
|
||||
| IORESOURCE_IRQ | IORESOURCE_DMA);
|
||||
excite_nand_resource.flags = excite_nand_resource.parent->flags &
|
||||
( IORESOURCE_IO | IORESOURCE_MEM
|
||||
| IORESOURCE_IRQ | IORESOURCE_DMA);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(excite_setup_devs);
|
||||
|
||||
294
arch/mips/basler/excite/excite_flashtest.c
Normal file
294
arch/mips/basler/excite/excite_flashtest.c
Normal file
@ -0,0 +1,294 @@
|
||||
/*
|
||||
* Copyright (C) 2005 by Basler Vision Technologies AG
|
||||
* Author: Thies Moeller <thies.moeller@baslerweb.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <excite.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <asm/rm9k-ocd.h> // for ocd_write
|
||||
#include <linux/workqueue.h> // for queue
|
||||
|
||||
#include "excite_nandflash.h"
|
||||
#include "nandflash.h"
|
||||
|
||||
#define PFX "excite flashtest: "
|
||||
typedef void __iomem *io_reg_t;
|
||||
|
||||
#define io_readb(__a__) __raw_readb((__a__))
|
||||
#define io_writeb(__v__, __a__) __raw_writeb((__v__), (__a__))
|
||||
|
||||
|
||||
|
||||
static inline const struct resource *excite_nandflash_get_resource(
|
||||
struct platform_device *d, unsigned long flags, const char *basename)
|
||||
{
|
||||
const char fmt[] = "%s_%u";
|
||||
char buf[80];
|
||||
|
||||
if (unlikely(snprintf(buf, sizeof buf, fmt, basename, d->id) >= sizeof buf))
|
||||
return NULL;
|
||||
|
||||
return platform_get_resource_byname(d, flags, buf);
|
||||
}
|
||||
|
||||
static inline io_reg_t
|
||||
excite_nandflash_map_regs(struct platform_device *d, const char *basename)
|
||||
{
|
||||
void *result = NULL;
|
||||
const struct resource *const r =
|
||||
excite_nandflash_get_resource(d, IORESOURCE_MEM, basename);
|
||||
if (r)
|
||||
result = ioremap_nocache(r->start, r->end + 1 - r->start);
|
||||
return result;
|
||||
}
|
||||
|
||||
/* controller and mtd information */
|
||||
|
||||
struct excite_nandflash_drvdata {
|
||||
struct mtd_info board_mtd;
|
||||
struct nand_chip board_chip;
|
||||
io_reg_t regs;
|
||||
};
|
||||
|
||||
|
||||
/* command and control functions */
|
||||
static void excite_nandflash_hwcontrol(struct mtd_info *mtd, int cmd)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
io_reg_t regs = container_of(mtd,struct excite_nandflash_drvdata,board_mtd)->regs;
|
||||
|
||||
switch (cmd) {
|
||||
/* Select the command latch */
|
||||
case NAND_CTL_SETCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_CMD;
|
||||
break;
|
||||
/* Deselect the command latch */
|
||||
case NAND_CTL_CLRCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
|
||||
break;
|
||||
/* Select the address latch */
|
||||
case NAND_CTL_SETALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_ADDR;
|
||||
break;
|
||||
/* Deselect the address latch */
|
||||
case NAND_CTL_CLRALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
|
||||
break;
|
||||
/* Select the chip -- not used */
|
||||
case NAND_CTL_SETNCE:
|
||||
break;
|
||||
/* Deselect the chip -- not used */
|
||||
case NAND_CTL_CLRNCE:
|
||||
break;
|
||||
}
|
||||
|
||||
this->IO_ADDR_R = this->IO_ADDR_W;
|
||||
}
|
||||
|
||||
/* excite_nandflash_devready()
|
||||
*
|
||||
* returns 0 if the nand is busy, 1 if it is ready
|
||||
*/
|
||||
static int excite_nandflash_devready(struct mtd_info *mtd)
|
||||
{
|
||||
struct excite_nandflash_drvdata *drvdata =
|
||||
container_of(mtd, struct excite_nandflash_drvdata, board_mtd);
|
||||
|
||||
return io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
|
||||
}
|
||||
|
||||
/* device management functions */
|
||||
|
||||
/* excite_nandflash_remove
|
||||
*
|
||||
* called by device layer to remove the driver
|
||||
* the binding to the mtd and all allocated
|
||||
* resources are released
|
||||
*/
|
||||
static int excite_nandflash_remove(struct device *dev)
|
||||
{
|
||||
struct excite_nandflash_drvdata *this = dev_get_drvdata(dev);
|
||||
|
||||
pr_info(PFX "remove");
|
||||
|
||||
dev_set_drvdata(dev, NULL);
|
||||
|
||||
if (this == NULL) {
|
||||
pr_debug(PFX "call remove without private data!!");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* free the common resources */
|
||||
if (this->regs != NULL) {
|
||||
iounmap(this->regs);
|
||||
this->regs = NULL;
|
||||
}
|
||||
|
||||
kfree(this);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int elapsed;
|
||||
|
||||
void my_workqueue_handler(void *arg)
|
||||
{
|
||||
elapsed = 1;
|
||||
}
|
||||
|
||||
DECLARE_WORK(sigElapsed, my_workqueue_handler, 0);
|
||||
|
||||
|
||||
/* excite_nandflash_probe
|
||||
*
|
||||
* called by device layer when it finds a device matching
|
||||
* one our driver can handled. This code checks to see if
|
||||
* it can allocate all necessary resources then calls the
|
||||
* nand layer to look for devices
|
||||
*/
|
||||
static int excite_nandflash_probe(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
|
||||
struct excite_nandflash_drvdata *drvdata; /* private driver data */
|
||||
struct nand_chip *board_chip; /* private flash chip data */
|
||||
struct mtd_info *board_mtd; /* mtd info for this board */
|
||||
|
||||
int err = 0;
|
||||
int count = 0;
|
||||
struct timeval tv,endtv;
|
||||
unsigned int dt;
|
||||
|
||||
pr_info(PFX "probe dev: (%p)\n", dev);
|
||||
|
||||
pr_info(PFX "adjust LB timing\n");
|
||||
ocd_writel(0x00000330, LDP2);
|
||||
|
||||
drvdata = kmalloc(sizeof(*drvdata), GFP_KERNEL);
|
||||
if (unlikely(!drvdata)) {
|
||||
printk(KERN_ERR PFX "no memory for drvdata\n");
|
||||
err = -ENOMEM;
|
||||
goto mem_error;
|
||||
}
|
||||
|
||||
/* Initialize structures */
|
||||
memset(drvdata, 0, sizeof(*drvdata));
|
||||
|
||||
/* bind private data into driver */
|
||||
dev_set_drvdata(dev, drvdata);
|
||||
|
||||
/* allocate and map the resource */
|
||||
drvdata->regs =
|
||||
excite_nandflash_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
|
||||
|
||||
if (unlikely(!drvdata->regs)) {
|
||||
printk(KERN_ERR PFX "cannot reserve register region\n");
|
||||
err = -ENXIO;
|
||||
goto io_error;
|
||||
}
|
||||
|
||||
/* initialise our chip */
|
||||
board_chip = &drvdata->board_chip;
|
||||
|
||||
board_chip->IO_ADDR_R = drvdata->regs + EXCITE_NANDFLASH_DATA;
|
||||
board_chip->IO_ADDR_W = drvdata->regs + EXCITE_NANDFLASH_DATA;
|
||||
|
||||
board_chip->hwcontrol = excite_nandflash_hwcontrol;
|
||||
board_chip->dev_ready = excite_nandflash_devready;
|
||||
|
||||
board_chip->chip_delay = 25;
|
||||
#if 0
|
||||
/* TODO: speedup the initial scan */
|
||||
board_chip->options = NAND_USE_FLASH_BBT;
|
||||
#endif
|
||||
board_chip->eccmode = NAND_ECC_SOFT;
|
||||
|
||||
/* link chip to mtd */
|
||||
board_mtd = &drvdata->board_mtd;
|
||||
board_mtd->priv = board_chip;
|
||||
|
||||
|
||||
pr_info(PFX "FlashTest\n");
|
||||
elapsed = 0;
|
||||
/* schedule_delayed_work(&sigElapsed, 1*HZ);
|
||||
while (!elapsed) {
|
||||
io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
|
||||
count++;
|
||||
}
|
||||
pr_info(PFX "reads in 1 sec --> %d\n",count);
|
||||
*/
|
||||
do_gettimeofday(&tv);
|
||||
for (count = 0 ; count < 1000000; count ++) {
|
||||
io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
|
||||
}
|
||||
do_gettimeofday(&endtv);
|
||||
dt = (endtv.tv_sec - tv.tv_sec) * 1000000 + endtv.tv_usec - tv.tv_usec;
|
||||
pr_info(PFX "%8d us timeval\n",dt);
|
||||
pr_info(PFX "EndFlashTest\n");
|
||||
|
||||
/* return with error to unload everything
|
||||
*/
|
||||
io_error:
|
||||
iounmap(drvdata->regs);
|
||||
|
||||
mem_error:
|
||||
kfree(drvdata);
|
||||
|
||||
if (err == 0)
|
||||
err = -EINVAL;
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct device_driver excite_nandflash_driver = {
|
||||
.name = "excite_nand",
|
||||
.bus = &platform_bus_type,
|
||||
.probe = excite_nandflash_probe,
|
||||
.remove = excite_nandflash_remove,
|
||||
};
|
||||
|
||||
static int __init excite_nandflash_init(void)
|
||||
{
|
||||
pr_info(PFX "register Driver (Rev: $Revision:$)\n");
|
||||
return driver_register(&excite_nandflash_driver);
|
||||
}
|
||||
|
||||
static void __exit excite_nandflash_exit(void)
|
||||
{
|
||||
driver_unregister(&excite_nandflash_driver);
|
||||
pr_info(PFX "Driver unregistered");
|
||||
}
|
||||
|
||||
module_init(excite_nandflash_init);
|
||||
module_exit(excite_nandflash_exit);
|
||||
|
||||
MODULE_AUTHOR("Thies Moeller <thies.moeller@baslerweb.com>");
|
||||
MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
80
arch/mips/basler/excite/excite_fpga.h
Normal file
80
arch/mips/basler/excite/excite_fpga.h
Normal file
@ -0,0 +1,80 @@
|
||||
#ifndef EXCITE_FPGA_H_INCLUDED
|
||||
#define EXCITE_FPGA_H_INCLUDED
|
||||
|
||||
|
||||
/**
|
||||
* Adress alignment of the individual FPGA bytes.
|
||||
* The address arrangement of the individual bytes of the FPGA is two
|
||||
* byte aligned at the embedded MK2 platform.
|
||||
*/
|
||||
#ifdef EXCITE_CCI_FPGA_MK2
|
||||
typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
|
||||
#else
|
||||
typedef unsigned char excite_cci_fpga_align_t;
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* Size of Dual Ported RAM.
|
||||
*/
|
||||
#define EXCITE_DPR_SIZE 263
|
||||
|
||||
|
||||
/**
|
||||
* Size of Reserved Status Fields in Dual Ported RAM.
|
||||
*/
|
||||
#define EXCITE_DPR_STATUS_SIZE 7
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* FPGA.
|
||||
* Hardware register layout of the FPGA interface. The FPGA must accessed
|
||||
* byte wise solely.
|
||||
* @see EXCITE_CCI_DPR_MK2
|
||||
*/
|
||||
typedef struct excite_fpga {
|
||||
|
||||
/**
|
||||
* Dual Ported RAM.
|
||||
*/
|
||||
excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
|
||||
|
||||
/**
|
||||
* Status.
|
||||
*/
|
||||
excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
|
||||
|
||||
#ifdef EXCITE_CCI_FPGA_MK2
|
||||
/**
|
||||
* RM9000 Interrupt.
|
||||
* Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
|
||||
*/
|
||||
excite_cci_fpga_align_t rm9k_int;
|
||||
#else
|
||||
/**
|
||||
* MK2 Interrupt.
|
||||
* Write access initiates interrupt at the ARM processor of the MK2.
|
||||
*/
|
||||
excite_cci_fpga_align_t mk2_int;
|
||||
|
||||
excite_cci_fpga_align_t gap[0x1000-0x10f];
|
||||
|
||||
/**
|
||||
* IRQ Source/Acknowledge.
|
||||
*/
|
||||
excite_cci_fpga_align_t rm9k_irq_src;
|
||||
|
||||
/**
|
||||
* IRQ Mask.
|
||||
* Set bits enable the related interrupt.
|
||||
*/
|
||||
excite_cci_fpga_align_t rm9k_irq_mask;
|
||||
#endif
|
||||
|
||||
|
||||
} excite_fpga;
|
||||
|
||||
|
||||
|
||||
#endif /* ndef EXCITE_FPGA_H_INCLUDED */
|
||||
183
arch/mips/basler/excite/excite_iodev.c
Normal file
183
arch/mips/basler/excite/excite_iodev.c
Normal file
@ -0,0 +1,183 @@
|
||||
/*
|
||||
* Copyright (C) 2005 by Basler Vision Technologies AG
|
||||
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/poll.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/miscdevice.h>
|
||||
|
||||
#include "excite_iodev.h"
|
||||
|
||||
|
||||
|
||||
static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
|
||||
static int __init iodev_probe(struct device *);
|
||||
static int __exit iodev_remove(struct device *);
|
||||
static int iodev_open(struct inode *, struct file *);
|
||||
static int iodev_release(struct inode *, struct file *);
|
||||
static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
|
||||
static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
|
||||
static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *);
|
||||
|
||||
|
||||
|
||||
static const char iodev_name[] = "iodev";
|
||||
static unsigned int iodev_irq;
|
||||
static DECLARE_WAIT_QUEUE_HEAD(wq);
|
||||
|
||||
|
||||
|
||||
static struct file_operations fops =
|
||||
{
|
||||
.owner = THIS_MODULE,
|
||||
.open = iodev_open,
|
||||
.release = iodev_release,
|
||||
.read = iodev_read,
|
||||
.poll = iodev_poll
|
||||
};
|
||||
|
||||
static struct miscdevice miscdev =
|
||||
{
|
||||
.minor = MISC_DYNAMIC_MINOR,
|
||||
.name = iodev_name,
|
||||
.fops = &fops
|
||||
};
|
||||
|
||||
static struct device_driver iodev_driver =
|
||||
{
|
||||
.name = (char *) iodev_name,
|
||||
.bus = &platform_bus_type,
|
||||
.owner = THIS_MODULE,
|
||||
.probe = iodev_probe,
|
||||
.remove = __exit_p(iodev_remove)
|
||||
};
|
||||
|
||||
|
||||
|
||||
static const struct resource *
|
||||
iodev_get_resource(struct platform_device *pdv, const char *name,
|
||||
unsigned int type)
|
||||
{
|
||||
char buf[80];
|
||||
if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
|
||||
return NULL;
|
||||
return platform_get_resource_byname(pdv, type, buf);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* No hotplugging on the platform bus - use __init */
|
||||
static int __init iodev_probe(struct device *dev)
|
||||
{
|
||||
struct platform_device * const pdv = to_platform_device(dev);
|
||||
const struct resource * const ri =
|
||||
iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
|
||||
|
||||
if (unlikely(!ri))
|
||||
return -ENXIO;
|
||||
|
||||
iodev_irq = ri->start;
|
||||
return misc_register(&miscdev);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int __exit iodev_remove(struct device *dev)
|
||||
{
|
||||
return misc_deregister(&miscdev);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int iodev_open(struct inode *i, struct file *f)
|
||||
{
|
||||
return request_irq(iodev_irq, iodev_irqhdl, SA_INTERRUPT,
|
||||
iodev_name, &miscdev);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int iodev_release(struct inode *i, struct file *f)
|
||||
{
|
||||
free_irq(iodev_irq, &miscdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static ssize_t
|
||||
iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
|
||||
{
|
||||
ssize_t ret;
|
||||
DEFINE_WAIT(w);
|
||||
|
||||
prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
|
||||
if (!signal_pending(current))
|
||||
schedule();
|
||||
ret = signal_pending(current) ? -ERESTARTSYS : 0;
|
||||
finish_wait(&wq, &w);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
|
||||
{
|
||||
poll_wait(f, &wq, p);
|
||||
return POLLOUT | POLLWRNORM;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
|
||||
{
|
||||
wake_up(&wq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int __init iodev_init_module(void)
|
||||
{
|
||||
return driver_register(&iodev_driver);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void __exit iodev_cleanup_module(void)
|
||||
{
|
||||
driver_unregister(&iodev_driver);
|
||||
}
|
||||
|
||||
module_init(iodev_init_module);
|
||||
module_exit(iodev_cleanup_module);
|
||||
|
||||
|
||||
|
||||
MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
|
||||
MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
|
||||
MODULE_VERSION("0.0");
|
||||
MODULE_LICENSE("GPL");
|
||||
10
arch/mips/basler/excite/excite_iodev.h
Normal file
10
arch/mips/basler/excite/excite_iodev.h
Normal file
@ -0,0 +1,10 @@
|
||||
#ifndef __EXCITE_IODEV_H__
|
||||
#define __EXCITE_IODEV_H__
|
||||
|
||||
/* Device name */
|
||||
#define IODEV_NAME "iodev"
|
||||
|
||||
/* Resource names */
|
||||
#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
|
||||
|
||||
#endif /* __EXCITE_IODEV_H__ */
|
||||
129
arch/mips/basler/excite/excite_irq.c
Normal file
129
arch/mips/basler/excite/excite_irq.c
Normal file
@ -0,0 +1,129 @@
|
||||
/*
|
||||
* Copyright (C) by Basler Vision Technologies AG
|
||||
* Author: Thomas Koeller <thomas.koeller@baslereb.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/random.h>
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/rm9k-ocd.h>
|
||||
|
||||
#include <excite.h>
|
||||
|
||||
extern asmlinkage void excite_handle_int(void);
|
||||
|
||||
/*
|
||||
* Initialize the interrupt handler
|
||||
*/
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
mips_cpu_irq_init(0);
|
||||
rm7k_cpu_irq_init(8);
|
||||
rm9k_cpu_irq_init(12);
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
excite_kgdb_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
{
|
||||
const u32
|
||||
interrupts = read_c0_cause() >> 8,
|
||||
mask = ((read_c0_status() >> 8) & 0x000000ff) |
|
||||
(read_c0_intcontrol() & 0x0000ff00),
|
||||
pending = interrupts & mask;
|
||||
u32 msgintflags, msgintmask, msgint;
|
||||
|
||||
/* process timer interrupt */
|
||||
if (pending & (1 << TIMER_IRQ)) {
|
||||
do_IRQ(TIMER_IRQ, regs);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Process PCI interrupts */
|
||||
#if USB_IRQ < 10
|
||||
msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
|
||||
msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
|
||||
msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
|
||||
if ((pending & (1 << USB_IRQ)) && msgint) {
|
||||
#else
|
||||
if (pending & (1 << USB_IRQ)) {
|
||||
#endif
|
||||
do_IRQ(USB_IRQ, regs);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Process TITAN interrupts */
|
||||
msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
|
||||
msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
|
||||
msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
|
||||
if ((pending & (1 << TITAN_IRQ)) && msgint) {
|
||||
ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
|
||||
#if defined(CONFIG_KGDB)
|
||||
excite_kgdb_inthdl(regs);
|
||||
#endif
|
||||
do_IRQ(TITAN_IRQ, regs);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Process FPGA line #0 interrupts */
|
||||
msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
|
||||
msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
|
||||
msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
|
||||
if ((pending & (1 << FPGA0_IRQ)) && msgint) {
|
||||
do_IRQ(FPGA0_IRQ, regs);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Process FPGA line #1 interrupts */
|
||||
msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
|
||||
msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
|
||||
msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
|
||||
if ((pending & (1 << FPGA1_IRQ)) && msgint) {
|
||||
do_IRQ(FPGA1_IRQ, regs);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Process PHY interrupts */
|
||||
msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
|
||||
msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
|
||||
msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
|
||||
if ((pending & (1 << PHY_IRQ)) && msgint) {
|
||||
do_IRQ(PHY_IRQ, regs);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Process spurious interrupts */
|
||||
spurious_interrupt(regs);
|
||||
}
|
||||
81
arch/mips/basler/excite/excite_procfs.c
Normal file
81
arch/mips/basler/excite/excite_procfs.c
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (C) 2004, 2005 by Basler Vision Technologies AG
|
||||
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
|
||||
*
|
||||
* Procfs support for Basler eXcite
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/stat.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/rm9k-ocd.h>
|
||||
|
||||
#include <excite.h>
|
||||
|
||||
static int excite_get_unit_id(char *buf, char **addr, off_t offs, int size)
|
||||
{
|
||||
const int len = snprintf(buf, PAGE_SIZE, "%06x", unit_id);
|
||||
const int w = len - offs;
|
||||
*addr = buf + offs;
|
||||
return w < size ? w : size;
|
||||
}
|
||||
|
||||
static int
|
||||
excite_bootrom_read(char *page, char **start, off_t off, int count,
|
||||
int *eof, void *data)
|
||||
{
|
||||
void __iomem * src;
|
||||
|
||||
if (off >= EXCITE_SIZE_BOOTROM) {
|
||||
*eof = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if ((off + count) > EXCITE_SIZE_BOOTROM)
|
||||
count = EXCITE_SIZE_BOOTROM - off;
|
||||
|
||||
src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
|
||||
if (src) {
|
||||
memcpy_fromio(page, src, count);
|
||||
iounmap(src);
|
||||
*start = page;
|
||||
} else {
|
||||
count = -ENOMEM;
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
void excite_procfs_init(void)
|
||||
{
|
||||
/* Create & populate /proc/excite */
|
||||
struct proc_dir_entry * const pdir = proc_mkdir("excite", &proc_root);
|
||||
if (pdir) {
|
||||
struct proc_dir_entry * e;
|
||||
|
||||
e = create_proc_info_entry("unit_id", S_IRUGO, pdir,
|
||||
excite_get_unit_id);
|
||||
if (e) e->size = 6;
|
||||
|
||||
e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
|
||||
excite_bootrom_read, NULL);
|
||||
if (e) e->size = EXCITE_SIZE_BOOTROM;
|
||||
}
|
||||
}
|
||||
148
arch/mips/basler/excite/excite_prom.c
Normal file
148
arch/mips/basler/excite/excite_prom.c
Normal file
@ -0,0 +1,148 @@
|
||||
/*
|
||||
* Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
|
||||
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
|
||||
* Manish Lachwani.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/string.h>
|
||||
|
||||
#include <excite.h>
|
||||
|
||||
/* This struct is used by Redboot to pass arguments to the kernel */
|
||||
typedef struct
|
||||
{
|
||||
char *name;
|
||||
char *val;
|
||||
} t_env_var;
|
||||
|
||||
struct parmblock {
|
||||
t_env_var memsize;
|
||||
t_env_var modetty0;
|
||||
t_env_var ethaddr;
|
||||
t_env_var env_end;
|
||||
char *argv[2];
|
||||
char text[0];
|
||||
};
|
||||
|
||||
static unsigned int prom_argc;
|
||||
static const char ** prom_argv;
|
||||
static const t_env_var * prom_env;
|
||||
|
||||
static void prom_halt(void) __attribute__((noreturn));
|
||||
static void prom_exit(void) __attribute__((noreturn));
|
||||
|
||||
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Basler eXcite";
|
||||
}
|
||||
|
||||
/*
|
||||
* Halt the system
|
||||
*/
|
||||
static void prom_halt(void)
|
||||
{
|
||||
printk(KERN_NOTICE "\n** System halted.\n");
|
||||
while (1)
|
||||
asm volatile (
|
||||
"\t.set\tmips3\n"
|
||||
"\twait\n"
|
||||
"\t.set\tmips0\n"
|
||||
);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset the CPU and re-enter Redboot
|
||||
*/
|
||||
static void prom_exit(void)
|
||||
{
|
||||
unsigned int i;
|
||||
volatile unsigned char * const flg =
|
||||
(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
|
||||
|
||||
/* Clear the watchdog reset flag, set the reboot flag */
|
||||
*flg &= ~0x01;
|
||||
*flg |= 0x80;
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
*(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
|
||||
iob();
|
||||
mdelay(1000);
|
||||
}
|
||||
|
||||
printk(KERN_NOTICE "Reset failed\n");
|
||||
prom_halt();
|
||||
}
|
||||
|
||||
static const char __init *prom_getenv(char *name)
|
||||
{
|
||||
const t_env_var * p;
|
||||
for (p = prom_env; p->name != NULL; p++)
|
||||
if(strcmp(name, p->name) == 0)
|
||||
break;
|
||||
return p->val;
|
||||
}
|
||||
|
||||
/*
|
||||
* Init routine which accepts the variables from Redboot
|
||||
*/
|
||||
void __init prom_init(void)
|
||||
{
|
||||
const struct parmblock * const pb = (struct parmblock *) fw_arg2;
|
||||
|
||||
prom_argc = fw_arg0;
|
||||
prom_argv = (const char **) fw_arg1;
|
||||
prom_env = &pb->memsize;
|
||||
|
||||
/* Callbacks for halt, restart */
|
||||
_machine_restart = (void (*)(char *)) prom_exit;
|
||||
_machine_halt = prom_halt;
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
/* copy command line */
|
||||
strcpy(arcs_cmdline, prom_argv[1]);
|
||||
memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
|
||||
strcpy(modetty, prom_getenv("modetty0"));
|
||||
#endif /* CONFIG_32BIT */
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
# error 64 bit support not implemented
|
||||
#endif /* CONFIG_64BIT */
|
||||
|
||||
mips_machgroup = MACH_GROUP_TITAN;
|
||||
mips_machtype = MACH_TITAN_EXCITE;
|
||||
}
|
||||
|
||||
/* This is called from free_initmem(), so we need to provide it */
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
307
arch/mips/basler/excite/excite_setup.c
Normal file
307
arch/mips/basler/excite/excite_setup.c
Normal file
@ -0,0 +1,307 @@
|
||||
/*
|
||||
* Copyright (C) 2004, 2005 by Basler Vision Technologies AG
|
||||
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
|
||||
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
|
||||
* Manish Lachwani.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/pgtable-32.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/rm9k-ocd.h>
|
||||
|
||||
#include <excite.h>
|
||||
|
||||
#define TITAN_UART_CLK 25000000
|
||||
|
||||
#if 1
|
||||
/* normal serial port assignment */
|
||||
#define REGBASE_SER0 0x0208
|
||||
#define REGBASE_SER1 0x0238
|
||||
#define MASK_SER0 0x1
|
||||
#define MASK_SER1 0x2
|
||||
#else
|
||||
/* serial ports swapped */
|
||||
#define REGBASE_SER0 0x0238
|
||||
#define REGBASE_SER1 0x0208
|
||||
#define MASK_SER0 0x2
|
||||
#define MASK_SER1 0x1
|
||||
#endif
|
||||
|
||||
unsigned long memsize;
|
||||
char modetty[30];
|
||||
unsigned int titan_irq = TITAN_IRQ;
|
||||
static void __iomem * ctl_regs;
|
||||
u32 unit_id;
|
||||
|
||||
volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
|
||||
volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
|
||||
|
||||
/* Protect access to shared GPI registers */
|
||||
spinlock_t titan_lock = SPIN_LOCK_UNLOCKED;
|
||||
int titan_irqflags;
|
||||
|
||||
|
||||
static void excite_timer_init(void)
|
||||
{
|
||||
const u32 modebit5 = ocd_readl(0x00e4);
|
||||
unsigned int
|
||||
mult = ((modebit5 >> 11) & 0x1f) + 2,
|
||||
div = ((modebit5 >> 16) & 0x1f) + 2;
|
||||
|
||||
if (div == 33) div = 1;
|
||||
mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
|
||||
}
|
||||
|
||||
static void excite_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
/* The eXcite platform uses the alternate timer interrupt */
|
||||
set_c0_intcontrol(0x80);
|
||||
setup_irq(TIMER_IRQ, irq);
|
||||
}
|
||||
|
||||
static int __init excite_init_console(void)
|
||||
{
|
||||
#if defined(CONFIG_SERIAL_8250)
|
||||
static __initdata char serr[] =
|
||||
KERN_ERR "Serial port #%u setup failed\n";
|
||||
struct uart_port up;
|
||||
|
||||
/* Take the DUART out of reset */
|
||||
titan_writel(0x00ff1cff, CPRR);
|
||||
|
||||
#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
|
||||
/* Enable both ports */
|
||||
titan_writel(MASK_SER0 | MASK_SER1, UACFG);
|
||||
#else
|
||||
/* Enable port #0 only */
|
||||
titan_writel(MASK_SER0, UACFG);
|
||||
#endif /* defined(CONFIG_KGDB) */
|
||||
|
||||
/*
|
||||
* Set up serial port #0. Do not use autodetection; the result is
|
||||
* not what we want.
|
||||
*/
|
||||
memset(&up, 0, sizeof(up));
|
||||
up.membase = (char *) titan_addr(REGBASE_SER0);
|
||||
up.irq = TITAN_IRQ;
|
||||
up.uartclk = TITAN_UART_CLK;
|
||||
up.regshift = 0;
|
||||
up.iotype = UPIO_MEM32;
|
||||
up.type = PORT_RM9000;
|
||||
up.flags = UPF_SHARE_IRQ;
|
||||
up.line = 0;
|
||||
if (early_serial_setup(&up))
|
||||
printk(serr, up.line);
|
||||
|
||||
#if CONFIG_SERIAL_8250_NR_UARTS > 1
|
||||
/* And now for port #1. */
|
||||
up.membase = (char *) titan_addr(REGBASE_SER1);
|
||||
up.line = 1;
|
||||
if (early_serial_setup(&up))
|
||||
printk(serr, up.line);
|
||||
#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
|
||||
#else
|
||||
/* Leave the DUART in reset */
|
||||
titan_writel(0x00ff3cff, CPRR);
|
||||
#endif /* defined(CONFIG_SERIAL_8250) */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init excite_platform_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned char buf[3];
|
||||
u8 reg;
|
||||
void __iomem * dpr;
|
||||
|
||||
/* BIU buffer allocations */
|
||||
ocd_writel(8, CPURSLMT); /* CPU */
|
||||
titan_writel(4, CPGRWL); /* GPI / Ethernet */
|
||||
|
||||
/* Map control registers located in FPGA */
|
||||
ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
|
||||
if (!ctl_regs)
|
||||
panic("eXcite: failed to map platform control registers\n");
|
||||
memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
|
||||
unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
|
||||
|
||||
/* Clear the reboot flag */
|
||||
dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
|
||||
reg = __raw_readb(dpr);
|
||||
__raw_writeb(reg & 0x7f, dpr);
|
||||
iounmap(dpr);
|
||||
|
||||
/* Interrupt controller setup */
|
||||
for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
|
||||
ocd_writel(0x00000000, i + 0x04);
|
||||
ocd_writel(0xffffffff, i + 0x0c);
|
||||
}
|
||||
ocd_writel(0x2, NMICONFIG);
|
||||
|
||||
ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
|
||||
INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
|
||||
ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
|
||||
| ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
|
||||
INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
|
||||
ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
|
||||
| ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
|
||||
INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
|
||||
ocd_writel((0x1 << (PHY_MSGINT % 0x20))
|
||||
| ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
|
||||
INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
|
||||
#if USB_IRQ < 10
|
||||
ocd_writel((0x1 << (USB_MSGINT % 0x20))
|
||||
| ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
|
||||
INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
|
||||
#endif
|
||||
/* Enable the packet FIFO, XDMA and XDMA arbiter */
|
||||
titan_writel(0x00ff18ff, CPRR);
|
||||
|
||||
/*
|
||||
* Set up the PADMUX. Power down all ethernet slices,
|
||||
* they will be powered up and configured at device startup.
|
||||
*/
|
||||
titan_writel(0x00878206, CPTC1R);
|
||||
titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
|
||||
|
||||
/* Reset and enable the FIFO block */
|
||||
titan_writel(0x00000001, SDRXFCIE);
|
||||
titan_writel(0x00000001, SDTXFCIE);
|
||||
titan_writel(0x00000100, SDRXFCIE);
|
||||
titan_writel(0x00000000, SDTXFCIE);
|
||||
|
||||
/*
|
||||
* Initialize the common interrupt shared by all components of
|
||||
* the GPI/Ethernet subsystem.
|
||||
*/
|
||||
titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
|
||||
titan_writel(TITAN_MSGINT, CPCFG1);
|
||||
|
||||
/*
|
||||
* XDMA configuration.
|
||||
* In order for the XDMA to be sharable among multiple drivers,
|
||||
* the setup must be done here in the platform. The reason is that
|
||||
* this setup can only be done while the XDMA is in reset. If this
|
||||
* were done in a driver, it would interrupt all other drivers
|
||||
* using the XDMA.
|
||||
*/
|
||||
titan_writel(0x80021dff, GXCFG); /* XDMA reset */
|
||||
titan_writel(0x00000000, CPXCISRA);
|
||||
titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
|
||||
#if defined (CONFIG_HIGHMEM)
|
||||
# error change for HIGHMEM support!
|
||||
#else
|
||||
titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
|
||||
#endif
|
||||
titan_writel(0, GXDMA_DESCADR);
|
||||
|
||||
for (i = 0x5040; i <= 0x5300; i += 0x0040)
|
||||
titan_writel(0x80080000, i); /* reset channel */
|
||||
|
||||
titan_writel((0x1 << 29) /* no sparse tx descr. */
|
||||
| (0x1 << 28) /* no sparse rx descr. */
|
||||
| (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
|
||||
| (0x1 << 21) | (0x1 << 22) /* data coherency */
|
||||
| (0x1 << 17)
|
||||
| 0x1dff,
|
||||
GXCFG);
|
||||
|
||||
#if defined(CONFIG_SMP)
|
||||
# error No SMP support
|
||||
#else
|
||||
/* All interrupts go to core #0 only. */
|
||||
titan_writel(0x1f007fff, CPDST0A);
|
||||
titan_writel(0x00000000, CPDST0B);
|
||||
titan_writel(0x0000ff3f, CPDST1A);
|
||||
titan_writel(0x00000000, CPDST1B);
|
||||
titan_writel(0x00ffffff, CPXDSTA);
|
||||
titan_writel(0x00000000, CPXDSTB);
|
||||
#endif
|
||||
|
||||
/* Enable DUART interrupts, disable everything else. */
|
||||
titan_writel(0x04000000, CPGIG0ER);
|
||||
titan_writel(0x000000c0, CPGIG1ER);
|
||||
|
||||
excite_procfs_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init plat_setup(void)
|
||||
{
|
||||
volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
|
||||
|
||||
/* Announce RAM to system */
|
||||
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
|
||||
|
||||
/* Set up timer initialization hooks */
|
||||
board_time_init = excite_timer_init;
|
||||
board_timer_setup = excite_timer_setup;
|
||||
|
||||
/* Set up the peripheral address map */
|
||||
*(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
|
||||
*(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
|
||||
*(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
|
||||
*(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
|
||||
wmb();
|
||||
*(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
|
||||
wmb();
|
||||
|
||||
ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
|
||||
ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
|
||||
ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
|
||||
ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
|
||||
|
||||
/* Local bus slot #0 */
|
||||
ocd_writel(0x00040510, LDP0);
|
||||
ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
|
||||
ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
|
||||
|
||||
/* Local bus slot #2 */
|
||||
ocd_writel(0x00000330, LDP2);
|
||||
ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
|
||||
ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
|
||||
|
||||
/* Local bus slot #3 */
|
||||
ocd_writel(0x00123413, LDP3);
|
||||
ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
|
||||
ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
|
||||
}
|
||||
|
||||
|
||||
|
||||
console_initcall(excite_init_console);
|
||||
arch_initcall(excite_platform_init);
|
||||
|
||||
EXPORT_SYMBOL(titan_lock);
|
||||
EXPORT_SYMBOL(titan_irqflags);
|
||||
EXPORT_SYMBOL(titan_irq);
|
||||
EXPORT_SYMBOL(ocd_base);
|
||||
EXPORT_SYMBOL(titan_base);
|
||||
1211
arch/mips/configs/excite_defconfig
Normal file
1211
arch/mips/configs/excite_defconfig
Normal file
File diff suppressed because it is too large
Load Diff
@ -23,6 +23,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
|
||||
#
|
||||
# These are still pretty much in the old state, watch, go blind.
|
||||
#
|
||||
obj-$(CONFIG_BASLER_EXCITE) = ops-titan.o pci-excite.o fixup-excite.o
|
||||
obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
|
||||
obj-$(CONFIG_LASAT) += pci-lasat.o
|
||||
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
|
||||
|
||||
36
arch/mips/pci/fixup-excite.c
Normal file
36
arch/mips/pci/fixup-excite.c
Normal file
@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (C) 2004 by Basler Vision Technologies AG
|
||||
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <excite.h>
|
||||
|
||||
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
if (pin == 0)
|
||||
return -1;
|
||||
|
||||
return USB_IRQ; /* USB controller is the only PCI device */
|
||||
}
|
||||
|
||||
/* Do platform specific device initialization at pci_enable_device() time */
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@ -26,8 +26,19 @@
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <asm/titan_dep.h>
|
||||
#include <asm/pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/rm9k-ocd.h>
|
||||
|
||||
/*
|
||||
* PCI specific defines
|
||||
*/
|
||||
#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
|
||||
#define TITAN_PCI_0_CONFIG_DATA 0x784
|
||||
|
||||
/*
|
||||
* Titan PCI Config Read Byte
|
||||
*/
|
||||
static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
|
||||
int size, u32 * val)
|
||||
{
|
||||
@ -43,8 +54,8 @@ static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
|
||||
|
||||
|
||||
/* start the configuration cycle */
|
||||
TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
|
||||
tmp = TITAN_READ(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
|
||||
ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
|
||||
tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
@ -71,20 +82,20 @@ static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
|
||||
(reg & 0xfc) | 0x80000000;
|
||||
|
||||
/* start the configuration cycle */
|
||||
TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
|
||||
ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
|
||||
|
||||
/* write the data */
|
||||
switch (size) {
|
||||
case 1:
|
||||
TITAN_WRITE_8(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3), val);
|
||||
ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
|
||||
break;
|
||||
|
||||
case 2:
|
||||
TITAN_WRITE_16(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2), val);
|
||||
ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
|
||||
break;
|
||||
|
||||
case 4:
|
||||
TITAN_WRITE(TITAN_PCI_0_CONFIG_DATA, val);
|
||||
ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
149
arch/mips/pci/pci-excite.c
Normal file
149
arch/mips/pci/pci-excite.c
Normal file
@ -0,0 +1,149 @@
|
||||
/*
|
||||
* Copyright (C) 2004 by Basler Vision Technologies AG
|
||||
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
|
||||
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/rm9k-ocd.h>
|
||||
#include <excite.h>
|
||||
|
||||
|
||||
extern struct pci_ops titan_pci_ops;
|
||||
|
||||
|
||||
static struct resource
|
||||
mem_resource = {
|
||||
.name = "PCI memory",
|
||||
.start = EXCITE_PHYS_PCI_MEM,
|
||||
.end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
|
||||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
io_resource = {
|
||||
.name = "PCI I/O",
|
||||
.start = EXCITE_PHYS_PCI_IO,
|
||||
.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
|
||||
static struct pci_controller bx_controller = {
|
||||
.pci_ops = &titan_pci_ops,
|
||||
.mem_resource = &mem_resource,
|
||||
.mem_offset = 0x00000000UL,
|
||||
.io_resource = &io_resource,
|
||||
.io_offset = 0x00000000UL
|
||||
};
|
||||
|
||||
|
||||
static char
|
||||
iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
|
||||
modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
|
||||
|
||||
#define RM9000x2_OCD_HTSC 0x0604
|
||||
#define RM9000x2_OCD_HTBHL 0x060c
|
||||
#define RM9000x2_OCD_PCIHRST 0x078c
|
||||
|
||||
#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
|
||||
#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
|
||||
|
||||
#define PCISC_FB2B 0x00000200
|
||||
#define PCISC_MWICG 0x00000010
|
||||
#define PCISC_EMC 0x00000004
|
||||
#define PCISC_ERMA 0x00000002
|
||||
|
||||
|
||||
|
||||
static int __init basler_excite_pci_setup(void)
|
||||
{
|
||||
const unsigned int fullbars = memsize / (256 << 20);
|
||||
unsigned int i;
|
||||
|
||||
/* Check modebits to see if PCI is really enabled. */
|
||||
if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
|
||||
panic(modebits_no_pci);
|
||||
|
||||
if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
|
||||
"Memory-mapped PCI I/O page"))
|
||||
panic(iopage_failed);
|
||||
|
||||
/* Enable PCI 0 as master for config cycles */
|
||||
ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
|
||||
|
||||
|
||||
/* Set up latency timer */
|
||||
ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
|
||||
|
||||
/* Setup host IO and Memory space */
|
||||
ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
|
||||
ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
|
||||
ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
|
||||
ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
|
||||
|
||||
/* Set up PCI BARs to map all installed memory */
|
||||
for (i = 0; i < 6; i++) {
|
||||
const unsigned int bar = 0x610 + i * 4;
|
||||
|
||||
if (i < fullbars) {
|
||||
ocd_writel(0x10000000 * i, bar);
|
||||
ocd_writel(0x01000000 * i, bar + 0x140);
|
||||
ocd_writel(0x0ffff029, bar + 0x100);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (i == fullbars) {
|
||||
int o;
|
||||
u32 mask;
|
||||
|
||||
const unsigned long rem = memsize - i * 0x10000000;
|
||||
if (!rem) {
|
||||
ocd_writel(0x00000000, bar + 0x100);
|
||||
continue;
|
||||
}
|
||||
|
||||
o = ffs(rem) - 1;
|
||||
if (rem & ~(0x1 << o))
|
||||
o++;
|
||||
mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
|
||||
ocd_writel(0x10000000 * i, bar);
|
||||
ocd_writel(0x01000000 * i, bar + 0x140);
|
||||
ocd_writel(0x00000029 | mask, bar + 0x100);
|
||||
continue;
|
||||
}
|
||||
|
||||
ocd_writel(0x00000000, bar + 0x100);
|
||||
}
|
||||
|
||||
/* Finally, enable the PCI interupt */
|
||||
#if USB_IRQ > 7
|
||||
set_c0_intcontrol(1 << USB_IRQ);
|
||||
#else
|
||||
set_c0_status(1 << (USB_IRQ + 8));
|
||||
#endif
|
||||
|
||||
ioport_resource.start = EXCITE_PHYS_PCI_IO;
|
||||
ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
|
||||
set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
|
||||
register_pci_controller(&bx_controller);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
arch_initcall(basler_excite_pci_setup);
|
||||
@ -217,6 +217,7 @@
|
||||
*/
|
||||
#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
|
||||
#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
|
||||
#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
|
||||
|
||||
/*
|
||||
* Valid machtype for group NEC EMMA2RH
|
||||
|
||||
40
include/asm-mips/mach-excite/cpu-feature-overrides.h
Normal file
40
include/asm-mips/mach-excite/cpu-feature-overrides.h
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
|
||||
*/
|
||||
#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
/*
|
||||
* Basler eXcite has an RM9122 processor.
|
||||
*/
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_has_mips16 0
|
||||
#define cpu_has_divec 0
|
||||
#define cpu_has_vce 0
|
||||
#define cpu_has_cache_cdex_p 0
|
||||
#define cpu_has_cache_cdex_s 0
|
||||
#define cpu_has_prefetch 1
|
||||
#define cpu_has_mcheck 0
|
||||
#define cpu_has_ejtag 0
|
||||
|
||||
#define cpu_has_llsc 1
|
||||
#define cpu_has_vtag_icache 0
|
||||
#define cpu_has_dc_aliases 0
|
||||
#define cpu_has_ic_fills_f_dc 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_icache_snoops_remote_store 0
|
||||
|
||||
#define cpu_has_nofpuex 0
|
||||
#define cpu_has_64bits 1
|
||||
|
||||
#define cpu_has_subset_pcaches 0
|
||||
|
||||
#define cpu_dcache_line_size() 32
|
||||
#define cpu_icache_line_size() 32
|
||||
#define cpu_scache_line_size() 32
|
||||
|
||||
#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
|
||||
155
include/asm-mips/mach-excite/excite.h
Normal file
155
include/asm-mips/mach-excite/excite.h
Normal file
@ -0,0 +1,155 @@
|
||||
#ifndef __EXCITE_H__
|
||||
#define __EXCITE_H__
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
#define EXCITE_CPU_EXT_CLOCK 100000000
|
||||
|
||||
#if !defined(__ASSEMBLER__)
|
||||
void __init excite_kgdb_init(void);
|
||||
void excite_procfs_init(void);
|
||||
extern unsigned long memsize;
|
||||
extern char modetty[];
|
||||
extern u32 unit_id;
|
||||
#endif
|
||||
|
||||
/* Base name for XICAP devices */
|
||||
#define XICAP_NAME "xicap_gpi"
|
||||
|
||||
/* OCD register offsets */
|
||||
#define LKB0 0x0038
|
||||
#define LKB5 0x0128
|
||||
#define LKM5 0x012C
|
||||
#define LKB7 0x0138
|
||||
#define LKM7 0x013c
|
||||
#define LKB8 0x0140
|
||||
#define LKM8 0x0144
|
||||
#define LKB9 0x0148
|
||||
#define LKM9 0x014c
|
||||
#define LKB10 0x0150
|
||||
#define LKM10 0x0154
|
||||
#define LKB11 0x0158
|
||||
#define LKM11 0x015c
|
||||
#define LKB12 0x0160
|
||||
#define LKM12 0x0164
|
||||
#define LKB13 0x0168
|
||||
#define LKM13 0x016c
|
||||
#define LDP0 0x0200
|
||||
#define LDP1 0x0210
|
||||
#define LDP2 0x0220
|
||||
#define LDP3 0x0230
|
||||
#define INTPIN0 0x0A40
|
||||
#define INTPIN1 0x0A44
|
||||
#define INTPIN2 0x0A48
|
||||
#define INTPIN3 0x0A4C
|
||||
#define INTPIN4 0x0A50
|
||||
#define INTPIN5 0x0A54
|
||||
#define INTPIN6 0x0A58
|
||||
#define INTPIN7 0x0A5C
|
||||
|
||||
|
||||
|
||||
|
||||
/* TITAN register offsets */
|
||||
#define CPRR 0x0004
|
||||
#define CPDSR 0x0008
|
||||
#define CPTC0R 0x000c
|
||||
#define CPTC1R 0x0010
|
||||
#define CPCFG0 0x0020
|
||||
#define CPCFG1 0x0024
|
||||
#define CPDST0A 0x0028
|
||||
#define CPDST0B 0x002c
|
||||
#define CPDST1A 0x0030
|
||||
#define CPDST1B 0x0034
|
||||
#define CPXDSTA 0x0038
|
||||
#define CPXDSTB 0x003c
|
||||
#define CPXCISRA 0x0048
|
||||
#define CPXCISRB 0x004c
|
||||
#define CPGIG0ER 0x0050
|
||||
#define CPGIG1ER 0x0054
|
||||
#define CPGRWL 0x0068
|
||||
#define CPURSLMT 0x00f8
|
||||
#define UACFG 0x0200
|
||||
#define UAINTS 0x0204
|
||||
#define SDRXFCIE 0x4828
|
||||
#define SDTXFCIE 0x4928
|
||||
#define INTP0Status0 0x1B00
|
||||
#define INTP0Mask0 0x1B04
|
||||
#define INTP0Set0 0x1B08
|
||||
#define INTP0Clear0 0x1B0C
|
||||
#define GXCFG 0x5000
|
||||
#define GXDMADRPFX 0x5018
|
||||
#define GXDMA_DESCADR 0x501c
|
||||
#define GXCH0TDESSTRT 0x5054
|
||||
|
||||
/* IRQ definitions */
|
||||
#define NMICONFIG 0xac0
|
||||
#define TITAN_MSGINT 0xc4
|
||||
#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
|
||||
#define FPGA0_MSGINT 0x5a
|
||||
#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
|
||||
#define FPGA1_MSGINT 0x7b
|
||||
#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
|
||||
#define PHY_MSGINT 0x9c
|
||||
#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
|
||||
|
||||
#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
|
||||
/* Pre-release units used interrupt pin #9 */
|
||||
#define USB_IRQ 11
|
||||
#else
|
||||
/* Re-designed units use interrupt pin #1 */
|
||||
#define USB_MSGINT 0x39
|
||||
#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
|
||||
#endif
|
||||
#define TIMER_IRQ 12
|
||||
|
||||
|
||||
/* Device address ranges */
|
||||
#define EXCITE_OFFS_OCD 0x1fffc000
|
||||
#define EXCITE_SIZE_OCD (16 * 1024)
|
||||
#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
|
||||
#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
|
||||
|
||||
#define EXCITE_OFFS_SCRAM 0x1fffa000
|
||||
#define EXCITE_SIZE_SCRAM (8 << 10)
|
||||
#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
|
||||
#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
|
||||
|
||||
#define EXCITE_OFFS_PCI_IO 0x1fff8000
|
||||
#define EXCITE_SIZE_PCI_IO (8 << 10)
|
||||
#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
|
||||
#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
|
||||
|
||||
#define EXCITE_OFFS_TITAN 0x1fff0000
|
||||
#define EXCITE_SIZE_TITAN (32 << 10)
|
||||
#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
|
||||
#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
|
||||
|
||||
#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
|
||||
#define EXCITE_SIZE_PCI_MEM (64 << 10)
|
||||
#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
|
||||
#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
|
||||
|
||||
#define EXCITE_OFFS_FPGA 0x1ffdc000
|
||||
#define EXCITE_SIZE_FPGA (16 << 10)
|
||||
#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
|
||||
#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
|
||||
|
||||
#define EXCITE_OFFS_NAND 0x1ffd8000
|
||||
#define EXCITE_SIZE_NAND (16 << 10)
|
||||
#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
|
||||
#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
|
||||
|
||||
#define EXCITE_OFFS_BOOTROM 0x1f000000
|
||||
#define EXCITE_SIZE_BOOTROM (8 << 20)
|
||||
#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
|
||||
#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
|
||||
|
||||
/* FPGA address offsets */
|
||||
#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
|
||||
#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
|
||||
|
||||
#endif /* __EXCITE_H__ */
|
||||
7
include/asm-mips/mach-excite/excite_nandflash.h
Normal file
7
include/asm-mips/mach-excite/excite_nandflash.h
Normal file
@ -0,0 +1,7 @@
|
||||
#ifndef __EXCITE_NANDFLASH_H__
|
||||
#define __EXCITE_NANDFLASH_H__
|
||||
|
||||
/* Resource names */
|
||||
#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
|
||||
|
||||
#endif /* __EXCITE_NANDFLASH_H__ */
|
||||
23
include/asm-mips/mach-excite/rm9k_eth.h
Normal file
23
include/asm-mips/mach-excite/rm9k_eth.h
Normal file
@ -0,0 +1,23 @@
|
||||
#if !defined(__RM9K_ETH_H__)
|
||||
#define __RM9K_ETH_H__
|
||||
|
||||
#define RM9K_GE_NAME "rm9k_ge"
|
||||
|
||||
/* Resource names */
|
||||
#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
|
||||
#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
|
||||
#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
|
||||
#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
|
||||
#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
|
||||
#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
|
||||
#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
|
||||
#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
|
||||
#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
|
||||
#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
|
||||
#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
|
||||
#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
|
||||
#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
|
||||
#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
|
||||
#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
|
||||
|
||||
#endif /* !defined(__RM9K_ETH_H__) */
|
||||
12
include/asm-mips/mach-excite/rm9k_wdt.h
Normal file
12
include/asm-mips/mach-excite/rm9k_wdt.h
Normal file
@ -0,0 +1,12 @@
|
||||
#ifndef __RM9K_WDT_H__
|
||||
#define __RM9K_WDT_H__
|
||||
|
||||
/* Device name */
|
||||
#define WDT_NAME "wdt_gpi"
|
||||
|
||||
/* Resource names */
|
||||
#define WDT_RESOURCE_REGS "excite_watchdog_regs"
|
||||
#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
|
||||
#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
|
||||
|
||||
#endif /* __RM9K_WDT_H__ */
|
||||
16
include/asm-mips/mach-excite/rm9k_xicap.h
Normal file
16
include/asm-mips/mach-excite/rm9k_xicap.h
Normal file
@ -0,0 +1,16 @@
|
||||
#ifndef __EXCITE_XICAP_H__
|
||||
#define __EXCITE_XICAP_H__
|
||||
|
||||
|
||||
/* Resource names */
|
||||
#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
|
||||
#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
|
||||
#define XICAP_RESOURCE_XDMA "xicap_xdma"
|
||||
#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
|
||||
#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
|
||||
#define XICAP_RESOURCE_IRQ "xicap_irq"
|
||||
#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
|
||||
#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
|
||||
#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
|
||||
|
||||
#endif /* __EXCITE_XICAP_H__ */
|
||||
56
include/asm-mips/rm9k-ocd.h
Normal file
56
include/asm-mips/rm9k-ocd.h
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (C) 2004 by Basler Vision Technologies AG
|
||||
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#if !defined(_ASM_RM9K_OCD_H)
|
||||
#define _ASM_RM9K_OCD_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
extern volatile void __iomem * const ocd_base;
|
||||
extern volatile void __iomem * const titan_base;
|
||||
|
||||
#define ocd_addr(__x__) (ocd_base + (__x__))
|
||||
#define titan_addr(__x__) (titan_base + (__x__))
|
||||
#define scram_addr(__x__) (scram_base + (__x__))
|
||||
|
||||
/* OCD register access */
|
||||
#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
|
||||
#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
|
||||
#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
|
||||
#define ocd_writel(__val__, __offs__) \
|
||||
__raw_writel((__val__), ocd_addr(__offs__))
|
||||
#define ocd_writew(__val__, __offs__) \
|
||||
__raw_writew((__val__), ocd_addr(__offs__))
|
||||
#define ocd_writeb(__val__, __offs__) \
|
||||
__raw_writeb((__val__), ocd_addr(__offs__))
|
||||
|
||||
/* TITAN register access - 32 bit-wide only */
|
||||
#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
|
||||
#define titan_writel(__val__, __offs__) \
|
||||
__raw_writel((__val__), titan_addr(__offs__))
|
||||
|
||||
/* Protect access to shared TITAN registers */
|
||||
extern spinlock_t titan_lock;
|
||||
extern int titan_irqflags;
|
||||
#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
|
||||
#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
|
||||
|
||||
#endif /* !defined(_ASM_RM9K_OCD_H) */
|
||||
@ -172,7 +172,8 @@
|
||||
* On the RM9000 there is a problem which makes the CreateDirtyExclusive
|
||||
* cache operation unusable on SMP systems.
|
||||
*/
|
||||
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
|
||||
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
|
||||
defined(CONFIG_BASLER_EXCITE)
|
||||
#define RM9000_CDEX_SMP_WAR 1
|
||||
#endif
|
||||
|
||||
@ -182,7 +183,7 @@
|
||||
* being fetched may case spurious exceptions.
|
||||
*/
|
||||
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
|
||||
defined(CONFIG_PMC_YOSEMITE)
|
||||
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 1
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user