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https://github.com/edk2-porting/linux-next.git
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Merge branch 'for-linus' into for-next
This commit is contained in:
commit
34e72afe73
@ -22,6 +22,8 @@ Optional Properties:
|
||||
- pclkN, clkN: Pairs of parent of input clock and input clock to the
|
||||
devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
|
||||
are supported currently.
|
||||
- power-domains: phandle pointing to the parent power domain, for more details
|
||||
see Documentation/devicetree/bindings/power/power_domain.txt
|
||||
|
||||
Node of a device using power domains must have a power-domains property
|
||||
defined with a phandle to respective power domain.
|
||||
|
@ -13,6 +13,10 @@ Boards with the ST STiH407 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih407";
|
||||
|
||||
Boards with the ST STiH410 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih410";
|
||||
|
||||
Boards with the ST STiH418 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih418";
|
||||
|
@ -4,7 +4,10 @@ Ethernet nodes are defined to describe on-chip ethernet interfaces in
|
||||
APM X-Gene SoC.
|
||||
|
||||
Required properties for all the ethernet interfaces:
|
||||
- compatible: Should be "apm,xgene-enet"
|
||||
- compatible: Should state binding information from the following list,
|
||||
- "apm,xgene-enet": RGMII based 1G interface
|
||||
- "apm,xgene1-sgenet": SGMII based 1G interface
|
||||
- "apm,xgene1-xgenet": XFI based 10G interface
|
||||
- reg: Address and length of the register set for the device. It contains the
|
||||
information of registers in the same order as described by reg-names
|
||||
- reg-names: Should contain the register set names
|
||||
|
@ -19,6 +19,16 @@ Required properties:
|
||||
providing multiple PM domains (e.g. power controllers), but can be any value
|
||||
as specified by device tree binding documentation of particular provider.
|
||||
|
||||
Optional properties:
|
||||
- power-domains : A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle.
|
||||
Some power domains might be powered from another power domain (or have
|
||||
other hardware specific dependencies). For representing such dependency
|
||||
a standard PM domain consumer binding is used. When provided, all domains
|
||||
created by the given provider should be subdomains of the domain
|
||||
specified by this binding. More details about power domain specifier are
|
||||
available in the next section.
|
||||
|
||||
Example:
|
||||
|
||||
power: power-controller@12340000 {
|
||||
@ -30,6 +40,25 @@ Example:
|
||||
The node above defines a power controller that is a PM domain provider and
|
||||
expects one cell as its phandle argument.
|
||||
|
||||
Example 2:
|
||||
|
||||
parent: power-controller@12340000 {
|
||||
compatible = "foo,power-controller";
|
||||
reg = <0x12340000 0x1000>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
child: power-controller@12340000 {
|
||||
compatible = "foo,power-controller";
|
||||
reg = <0x12341000 0x1000>;
|
||||
power-domains = <&parent 0>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
The nodes above define two power controllers: 'parent' and 'child'.
|
||||
Domains created by the 'child' power controller are subdomains of '0' power
|
||||
domain provided by the 'parent' power controller.
|
||||
|
||||
==PM domain consumers==
|
||||
|
||||
Required properties:
|
||||
|
@ -0,0 +1,19 @@
|
||||
ETRAX FS UART
|
||||
|
||||
Required properties:
|
||||
- compatible : "axis,etraxfs-uart"
|
||||
- reg: offset and length of the register set for the device.
|
||||
- interrupts: device interrupt
|
||||
|
||||
Optional properties:
|
||||
- {dtr,dsr,ri,cd}-gpios: specify a GPIO for DTR/DSR/RI/CD
|
||||
line respectively.
|
||||
|
||||
Example:
|
||||
|
||||
serial@b00260000 {
|
||||
compatible = "axis,etraxfs-uart";
|
||||
reg = <0xb0026000 0x1000>;
|
||||
interrupts = <68>;
|
||||
status = "disabled";
|
||||
};
|
@ -12,6 +12,9 @@ I. For patch submitters
|
||||
|
||||
devicetree@vger.kernel.org
|
||||
|
||||
and Cc: the DT maintainers. Use scripts/get_maintainer.pl to identify
|
||||
all of the DT maintainers.
|
||||
|
||||
3) The Documentation/ portion of the patch should come in the series before
|
||||
the code implementing the binding.
|
||||
|
||||
|
@ -20,6 +20,7 @@ amlogic Amlogic, Inc.
|
||||
ams AMS AG
|
||||
amstaos AMS-Taos Inc.
|
||||
apm Applied Micro Circuits Corporation (APM)
|
||||
arasan Arasan Chip Systems
|
||||
arm ARM Ltd.
|
||||
armadeus ARMadeus Systems SARL
|
||||
asahi-kasei Asahi Kasei Corp.
|
||||
@ -27,6 +28,7 @@ atmel Atmel Corporation
|
||||
auo AU Optronics Corporation
|
||||
avago Avago Technologies
|
||||
avic Shanghai AVIC Optoelectronics Co., Ltd.
|
||||
axis Axis Communications AB
|
||||
bosch Bosch Sensortec GmbH
|
||||
brcm Broadcom Corporation
|
||||
buffalo Buffalo, Inc.
|
||||
|
@ -26,6 +26,11 @@ Optional properties:
|
||||
- atmel,disable : Should be present if you want to disable the watchdog.
|
||||
- atmel,idle-halt : Should be present if you want to stop the watchdog when
|
||||
entering idle state.
|
||||
CAUTION: This property should be used with care, it actually makes the
|
||||
watchdog not counting when the CPU is in idle state, therefore the
|
||||
watchdog reset time depends on mean CPU usage and will not reset at all
|
||||
if the CPU stop working while it is in idle state, which is probably
|
||||
not what you want.
|
||||
- atmel,dbg-halt : Should be present if you want to stop the watchdog when
|
||||
entering debug state.
|
||||
|
||||
|
17
MAINTAINERS
17
MAINTAINERS
@ -1030,6 +1030,16 @@ F: arch/arm/mach-mxs/
|
||||
F: arch/arm/boot/dts/imx*
|
||||
F: arch/arm/configs/imx*_defconfig
|
||||
|
||||
ARM/FREESCALE VYBRID ARM ARCHITECTURE
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
M: Sascha Hauer <kernel@pengutronix.de>
|
||||
R: Stefan Agner <stefan@agner.ch>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
|
||||
F: arch/arm/mach-imx/*vf610*
|
||||
F: arch/arm/boot/dts/vf*
|
||||
|
||||
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
@ -1188,6 +1198,7 @@ ARM/Marvell Dove/MV78xx0/Orion SOC support
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
M: Gregory Clement <gregory.clement@free-electrons.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-dove/
|
||||
@ -2107,7 +2118,6 @@ F: drivers/net/ethernet/broadcom/bnx2x/
|
||||
|
||||
BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
|
||||
M: Christian Daudt <bcm@fixthebug.org>
|
||||
M: Matt Porter <mporter@linaro.org>
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
T: git git://github.com/broadcom/mach-bcm
|
||||
@ -2369,8 +2379,9 @@ F: arch/x86/include/asm/tce.h
|
||||
|
||||
CAN NETWORK LAYER
|
||||
M: Oliver Hartkopp <socketcan@hartkopp.net>
|
||||
M: Marc Kleine-Budde <mkl@pengutronix.de>
|
||||
L: linux-can@vger.kernel.org
|
||||
W: http://gitorious.org/linux-can
|
||||
W: https://github.com/linux-can
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git
|
||||
S: Maintained
|
||||
@ -2386,7 +2397,7 @@ CAN NETWORK DRIVERS
|
||||
M: Wolfgang Grandegger <wg@grandegger.com>
|
||||
M: Marc Kleine-Budde <mkl@pengutronix.de>
|
||||
L: linux-can@vger.kernel.org
|
||||
W: http://gitorious.org/linux-can
|
||||
W: https://github.com/linux-can
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git
|
||||
S: Maintained
|
||||
|
2
Makefile
2
Makefile
@ -1,7 +1,7 @@
|
||||
VERSION = 4
|
||||
PATCHLEVEL = 0
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
EXTRAVERSION = -rc4
|
||||
NAME = Hurr durr I'ma sheep
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -150,6 +150,7 @@ machine-$(CONFIG_ARCH_BERLIN) += berlin
|
||||
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
|
||||
machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
|
||||
machine-$(CONFIG_ARCH_DAVINCI) += davinci
|
||||
machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
|
||||
machine-$(CONFIG_ARCH_DOVE) += dove
|
||||
machine-$(CONFIG_ARCH_EBSA110) += ebsa110
|
||||
machine-$(CONFIG_ARCH_EFM32) += efm32
|
||||
|
@ -301,3 +301,11 @@
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
cd-inverted;
|
||||
};
|
||||
|
||||
&aes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -24,11 +24,3 @@
|
||||
&mmc1 {
|
||||
vmmc-supply = <&ldo3_reg>;
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aes {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -328,6 +328,10 @@
|
||||
dual_emac_res_vlan = <3>;
|
||||
};
|
||||
|
||||
&phy_sel {
|
||||
rmii-clock-ext;
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
|
@ -99,7 +99,7 @@
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
@ -107,7 +107,7 @@
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
@ -115,7 +115,7 @@
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <2>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
@ -107,7 +107,7 @@
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
@ -115,7 +115,7 @@
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
@ -123,7 +123,7 @@
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <2>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
@ -131,7 +131,7 @@
|
||||
ehrpwm3_tbclk: ehrpwm3_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
@ -139,7 +139,7 @@
|
||||
ehrpwm4_tbclk: ehrpwm4_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
@ -147,7 +147,7 @@
|
||||
ehrpwm5_tbclk: ehrpwm5_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <6>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
@ -494,12 +494,12 @@
|
||||
|
||||
pinctrl_usart3_rts: usart3_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */
|
||||
<AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_usart3_cts: usart3_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
|
||||
<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -853,7 +853,7 @@
|
||||
};
|
||||
|
||||
usb1: gadget@fffa4000 {
|
||||
compatible = "atmel,at91rm9200-udc";
|
||||
compatible = "atmel,at91sam9260-udc";
|
||||
reg = <0xfffa4000 0x4000>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&udc_clk>, <&udpck>;
|
||||
@ -976,7 +976,6 @@
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -124,11 +124,12 @@
|
||||
};
|
||||
|
||||
usb1: gadget@fffa4000 {
|
||||
compatible = "atmel,at91rm9200-udc";
|
||||
compatible = "atmel,at91sam9261-udc";
|
||||
reg = <0xfffa4000 0x4000>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&udc_clk>, <&udpck>;
|
||||
clock-names = "usb_clk", "udc_clk", "udpck";
|
||||
clocks = <&udc_clk>, <&udpck>;
|
||||
clock-names = "pclk", "hclk";
|
||||
atmel,matrix = <&matrix>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -262,7 +263,7 @@
|
||||
};
|
||||
|
||||
matrix: matrix@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-bus-matrix";
|
||||
compatible = "atmel,at91sam9260-bus-matrix", "syscon";
|
||||
reg = <0xffffee00 0x200>;
|
||||
};
|
||||
|
||||
|
@ -69,7 +69,7 @@
|
||||
|
||||
sram1: sram@00500000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x4000>;
|
||||
reg = <0x00500000 0x4000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
@ -856,7 +856,7 @@
|
||||
};
|
||||
|
||||
usb1: gadget@fff78000 {
|
||||
compatible = "atmel,at91rm9200-udc";
|
||||
compatible = "atmel,at91sam9263-udc";
|
||||
reg = <0xfff78000 0x4000>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&udc_clk>, <&udpck>;
|
||||
@ -905,7 +905,6 @@
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1116,7 +1116,6 @@
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1301,7 +1300,7 @@
|
||||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00800000 0x100000>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
|
||||
clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -894,7 +894,6 @@
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -1066,7 +1066,7 @@
|
||||
reg = <0x00500000 0x80000
|
||||
0xf803c000 0x400>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&usb>, <&udphs_clk>;
|
||||
clocks = <&utmi>, <&udphs_clk>;
|
||||
clock-names = "hclk", "pclk";
|
||||
status = "disabled";
|
||||
|
||||
@ -1130,7 +1130,6 @@
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1186,7 +1185,7 @@
|
||||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00700000 0x100000>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
|
||||
clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -263,17 +263,15 @@
|
||||
|
||||
dcan1_pins_default: dcan1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
|
||||
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
|
||||
0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_sleep: dcan1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (MUX_MODE15) /* dcan1_tx.off */
|
||||
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
|
||||
0x418 (MUX_MODE15) /* wakeup0.off */
|
||||
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
@ -119,17 +119,15 @@
|
||||
|
||||
dcan1_pins_default: dcan1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
|
||||
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
|
||||
0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_sleep: dcan1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (MUX_MODE15) /* dcan1_tx.off */
|
||||
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
|
||||
0x418 (MUX_MODE15) /* wakeup0.off */
|
||||
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
|
||||
|
@ -243,10 +243,18 @@
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_core_byp_mux: dpll_core_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x012c>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-core-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
|
||||
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
|
||||
};
|
||||
|
||||
@ -309,10 +317,18 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_dsp_byp_mux: dpll_dsp_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x0240>;
|
||||
};
|
||||
|
||||
dpll_dsp_ck: dpll_dsp_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
|
||||
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
|
||||
};
|
||||
|
||||
@ -335,10 +351,18 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_iva_byp_mux: dpll_iva_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x01ac>;
|
||||
};
|
||||
|
||||
dpll_iva_ck: dpll_iva_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
|
||||
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
|
||||
};
|
||||
|
||||
@ -361,10 +385,18 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_gpu_byp_mux: dpll_gpu_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x02e4>;
|
||||
};
|
||||
|
||||
dpll_gpu_ck: dpll_gpu_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
|
||||
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
|
||||
};
|
||||
|
||||
@ -398,10 +430,18 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_ddr_byp_mux: dpll_ddr_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x021c>;
|
||||
};
|
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
|
||||
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
|
||||
};
|
||||
|
||||
@ -416,10 +456,18 @@
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_gmac_byp_mux: dpll_gmac_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x02b4>;
|
||||
};
|
||||
|
||||
dpll_gmac_ck: dpll_gmac_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
|
||||
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
|
||||
};
|
||||
|
||||
@ -482,10 +530,18 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_eve_byp_mux: dpll_eve_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x0290>;
|
||||
};
|
||||
|
||||
dpll_eve_ck: dpll_eve_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
|
||||
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
|
||||
};
|
||||
|
||||
@ -1249,10 +1305,18 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_per_byp_mux: dpll_per_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x014c>;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
|
||||
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
|
||||
};
|
||||
|
||||
@ -1275,10 +1339,18 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_usb_byp_mux: dpll_usb_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x018c>;
|
||||
};
|
||||
|
||||
dpll_usb_ck: dpll_usb_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-j-type-clock";
|
||||
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
|
||||
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
|
||||
};
|
||||
|
||||
|
@ -18,6 +18,7 @@
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
#include <dt-bindings/clock/exynos3250.h>
|
||||
|
||||
/ {
|
||||
@ -193,6 +194,7 @@
|
||||
interrupts = <0 216 0>;
|
||||
clocks = <&cmu CLK_TMU_APBIF>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
52
arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
Normal file
52
arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Device tree sources for Exynos4 thermal zone
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
thermal-sensors = <&tmu 0>;
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
cpu_alert0: cpu-alert-0 {
|
||||
temperature = <70000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu_alert1: cpu-alert-1 {
|
||||
temperature = <95000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu_alert2: cpu-alert-2 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu_crit0: cpu-crit-0 {
|
||||
temperature = <120000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu_alert1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
@ -38,6 +38,7 @@
|
||||
i2c5 = &i2c_5;
|
||||
i2c6 = &i2c_6;
|
||||
i2c7 = &i2c_7;
|
||||
i2c8 = &i2c_8;
|
||||
csis0 = &csis_0;
|
||||
csis1 = &csis_1;
|
||||
fimc0 = &fimc_0;
|
||||
@ -104,6 +105,7 @@
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10023C20 0x20>;
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&pd_lcd0>;
|
||||
};
|
||||
|
||||
pd_cam: cam-power-domain@10023C00 {
|
||||
@ -554,6 +556,22 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_8: i2c@138E0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-hdmiphy-i2c";
|
||||
reg = <0x138E0000 0x100>;
|
||||
interrupts = <0 93 0>;
|
||||
clocks = <&clock CLK_I2C_HDMI>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
|
||||
hdmi_i2c_phy: hdmiphy@38 {
|
||||
compatible = "exynos4210-hdmiphy";
|
||||
reg = <0x38>;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0: spi@13920000 {
|
||||
compatible = "samsung,exynos4210-spi";
|
||||
reg = <0x13920000 0x100>;
|
||||
@ -663,6 +681,33 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu: tmu@100C0000 {
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
hdmi: hdmi@12D00000 {
|
||||
compatible = "samsung,exynos4210-hdmi";
|
||||
reg = <0x12D00000 0x70000>;
|
||||
interrupts = <0 92 0>;
|
||||
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
|
||||
"mout_hdmi";
|
||||
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
||||
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
||||
<&clock CLK_MOUT_HDMI>;
|
||||
phy = <&hdmi_i2c_phy>;
|
||||
power-domains = <&pd_tv>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mixer: mixer@12C10000 {
|
||||
compatible = "samsung,exynos4210-mixer";
|
||||
interrupts = <0 91 0>;
|
||||
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
|
||||
power-domains = <&pd_tv>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_dmc0: ppmu_dmc0@106a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106a0000 0x2000>;
|
||||
|
@ -426,6 +426,25 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tmu@100C0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 800MHz at freq_table */
|
||||
cooling-device = <&cpu0 2 2>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz at freq_table */
|
||||
cooling-device = <&cpu0 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
camera {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <>;
|
||||
|
@ -505,6 +505,63 @@
|
||||
assigned-clock-rates = <0>, <160000000>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_en: voltage-regulator-hdmi-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "HDMI_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpe0 1 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c-ddc {
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&gpe4 2 0 &gpe4 3 0>;
|
||||
i2c-gpio,delay-us = <100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pinctrl-0 = <&i2c_ddc_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mixer@12C10000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hdmi@12D00000 {
|
||||
hpd-gpio = <&gpx3 7 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_hpd>;
|
||||
hdmi-en-supply = <&hdmi_en>;
|
||||
vdd-supply = <&ldo3_reg>;
|
||||
vdd_osc-supply = <&ldo4_reg>;
|
||||
vdd_pll-supply = <&ldo3_reg>;
|
||||
ddc = <&hdmi_ddc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@138E0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_1 {
|
||||
hdmi_hpd: hdmi-hpd {
|
||||
samsung,pins = "gpx3-7";
|
||||
samsung,pin-pud = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
i2c_ddc_bus: i2c-ddc-bus {
|
||||
samsung,pins = "gpe4-2", "gpe4-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdma1 {
|
||||
|
@ -21,6 +21,7 @@
|
||||
|
||||
#include "exynos4.dtsi"
|
||||
#include "exynos4210-pinctrl.dtsi"
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "samsung,exynos4210", "samsung,exynos4";
|
||||
@ -35,10 +36,13 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@900 {
|
||||
cpu0: cpu@900 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0x900>;
|
||||
cooling-min-level = <4>;
|
||||
cooling-max-level = <2>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu@901 {
|
||||
@ -153,16 +157,38 @@
|
||||
reg = <0x03860000 0x1000>;
|
||||
};
|
||||
|
||||
tmu@100C0000 {
|
||||
tmu: tmu@100C0000 {
|
||||
compatible = "samsung,exynos4210-tmu";
|
||||
interrupt-parent = <&combiner>;
|
||||
reg = <0x100C0000 0x100>;
|
||||
interrupts = <2 4>;
|
||||
clocks = <&clock CLK_TMU_APBIF>;
|
||||
clock-names = "tmu_apbif";
|
||||
samsung,tmu_gain = <15>;
|
||||
samsung,tmu_reference_voltage = <7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
||||
trips {
|
||||
cpu_alert0: cpu-alert-0 {
|
||||
temperature = <85000>; /* millicelsius */
|
||||
};
|
||||
cpu_alert1: cpu-alert-1 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
};
|
||||
cpu_alert2: cpu-alert-2 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
g2d@12800000 {
|
||||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
@ -203,6 +229,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
mixer: mixer@12C10000 {
|
||||
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
|
||||
"sclk_mixer";
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||||
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
|
||||
<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
|
||||
};
|
||||
|
||||
ppmu_lcd1: ppmu_lcd1@12240000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x12240000 0x2000>;
|
||||
|
@ -26,10 +26,13 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@A00 {
|
||||
cpu0: cpu@A00 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0xA00>;
|
||||
cooling-min-level = <13>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu@A01 {
|
||||
|
@ -249,6 +249,20 @@
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: ldo@8 {
|
||||
regulator-compatible = "LDO8";
|
||||
regulator-name = "VDD10_HDMI_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
ldo10_reg: ldo@10 {
|
||||
regulator-compatible = "LDO10";
|
||||
regulator-name = "VDDQ_MIPIHSI_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD18_ABB1_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
@ -411,6 +425,51 @@
|
||||
ehci: ehci@12580000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tmu@100C0000 {
|
||||
vtmu-supply = <&ldo10_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 800MHz at freq_table */
|
||||
cooling-device = <&cpu0 7 7>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz at freq_table */
|
||||
cooling-device = <&cpu0 13 13>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mixer: mixer@12C10000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hdmi@12D00000 {
|
||||
hpd-gpio = <&gpx3 7 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_hpd>;
|
||||
vdd-supply = <&ldo8_reg>;
|
||||
vdd_osc-supply = <&ldo10_reg>;
|
||||
vdd_pll-supply = <&ldo8_reg>;
|
||||
ddc = <&hdmi_ddc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c@13880000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_bus>;
|
||||
};
|
||||
|
||||
i2c@138E0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_1 {
|
||||
@ -425,4 +484,9 @@
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
hdmi_hpd: hdmi-hpd {
|
||||
samsung,pins = "gpx3-7";
|
||||
samsung,pin-pud = <1>;
|
||||
};
|
||||
};
|
||||
|
24
arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
Normal file
24
arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Device tree sources for Exynos4412 TMU sensor configuration
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal_exynos.h>
|
||||
|
||||
#thermal-sensor-cells = <0>;
|
||||
samsung,tmu_gain = <8>;
|
||||
samsung,tmu_reference_voltage = <16>;
|
||||
samsung,tmu_noise_cancel_mode = <4>;
|
||||
samsung,tmu_efuse_value = <55>;
|
||||
samsung,tmu_min_efuse_value = <40>;
|
||||
samsung,tmu_max_efuse_value = <100>;
|
||||
samsung,tmu_first_point_trim = <25>;
|
||||
samsung,tmu_second_point_trim = <85>;
|
||||
samsung,tmu_default_temp_offset = <50>;
|
||||
samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
|
@ -927,6 +927,21 @@
|
||||
pulldown-ohm = <100000>; /* 100K */
|
||||
io-channels = <&adc 2>; /* Battery temperature */
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 800MHz at freq_table */
|
||||
cooling-device = <&cpu0 7 7>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz at freq_table */
|
||||
cooling-device = <&cpu0 13 13>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_system_controller {
|
||||
|
@ -26,10 +26,13 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@A00 {
|
||||
cpu0: cpu@A00 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0xA00>;
|
||||
cooling-min-level = <13>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu@A01 {
|
||||
|
@ -19,6 +19,7 @@
|
||||
|
||||
#include "exynos4.dtsi"
|
||||
#include "exynos4x12-pinctrl.dtsi"
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
@ -297,4 +298,15 @@
|
||||
clock-names = "tmu_apbif";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi: hdmi@12D00000 {
|
||||
compatible = "samsung,exynos4212-hdmi";
|
||||
};
|
||||
|
||||
mixer: mixer@12C10000 {
|
||||
compatible = "samsung,exynos4212-mixer";
|
||||
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||||
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
|
||||
};
|
||||
};
|
||||
|
@ -20,7 +20,7 @@
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
#include "exynos5.dtsi"
|
||||
#include "exynos5250-pinctrl.dtsi"
|
||||
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
#include <dt-bindings/clock/exynos-audss-clk.h>
|
||||
|
||||
/ {
|
||||
@ -58,11 +58,14 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
clock-frequency = <1700000000>;
|
||||
cooling-min-level = <15>;
|
||||
cooling-max-level = <9>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
@ -102,6 +105,12 @@
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_disp1: disp1-power-domain@100440A0 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x100440A0 0x20>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
clock: clock-controller@10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
@ -235,12 +244,32 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu@10060000 {
|
||||
tmu: tmu@10060000 {
|
||||
compatible = "samsung,exynos5250-tmu";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 800MHz at freq_table */
|
||||
cooling-device = <&cpu0 9 9>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz at freq_table */
|
||||
cooling-device = <&cpu0 15 15>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
@ -719,6 +748,7 @@
|
||||
hdmi: hdmi {
|
||||
compatible = "samsung,exynos4212-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
power-domains = <&pd_disp1>;
|
||||
interrupts = <0 95 0>;
|
||||
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
||||
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
||||
@ -731,9 +761,11 @@
|
||||
mixer {
|
||||
compatible = "samsung,exynos5250-mixer";
|
||||
reg = <0x14450000 0x10000>;
|
||||
power-domains = <&pd_disp1>;
|
||||
interrupts = <0 94 0>;
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "sclk_hdmi";
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||||
<&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "hdmi", "sclk_hdmi";
|
||||
};
|
||||
|
||||
dp_phy: video-phy@10040720 {
|
||||
@ -743,6 +775,7 @@
|
||||
};
|
||||
|
||||
dp: dp-controller@145B0000 {
|
||||
power-domains = <&pd_disp1>;
|
||||
clocks = <&clock CLK_DP>;
|
||||
clock-names = "dp";
|
||||
phys = <&dp_phy>;
|
||||
@ -750,6 +783,7 @@
|
||||
};
|
||||
|
||||
fimd: fimd@14400000 {
|
||||
power-domains = <&pd_disp1>;
|
||||
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
};
|
||||
|
35
arch/arm/boot/dts/exynos5420-trip-points.dtsi
Normal file
35
arch/arm/boot/dts/exynos5420-trip-points.dtsi
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Device tree sources for default Exynos5420 thermal zone definition
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
cpu-alert-0 {
|
||||
temperature = <85000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu-alert-1 {
|
||||
temperature = <103000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu-alert-2 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu-crit-0 {
|
||||
temperature = <1200000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
@ -740,8 +740,9 @@
|
||||
compatible = "samsung,exynos5420-mixer";
|
||||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "sclk_hdmi";
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||||
<&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "hdmi", "sclk_hdmi";
|
||||
power-domains = <&disp_pd>;
|
||||
};
|
||||
|
||||
@ -782,6 +783,7 @@
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmu_cpu1: tmu@10064000 {
|
||||
@ -790,6 +792,7 @@
|
||||
interrupts = <0 183 0>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmu_cpu2: tmu@10068000 {
|
||||
@ -798,6 +801,7 @@
|
||||
interrupts = <0 184 0>;
|
||||
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmu_cpu3: tmu@1006c000 {
|
||||
@ -806,6 +810,7 @@
|
||||
interrupts = <0 185 0>;
|
||||
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmu_gpu: tmu@100a0000 {
|
||||
@ -814,6 +819,30 @@
|
||||
interrupts = <0 215 0>;
|
||||
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu0_thermal: cpu0-thermal {
|
||||
thermal-sensors = <&tmu_cpu0>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
cpu1_thermal: cpu1-thermal {
|
||||
thermal-sensors = <&tmu_cpu1>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
cpu2_thermal: cpu2-thermal {
|
||||
thermal-sensors = <&tmu_cpu2>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
cpu3_thermal: cpu3-thermal {
|
||||
thermal-sensors = <&tmu_cpu3>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
gpu_thermal: gpu-thermal {
|
||||
thermal-sensors = <&tmu_gpu>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
watchdog: watchdog@101D0000 {
|
||||
|
24
arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi
Normal file
24
arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Device tree sources for Exynos5440 TMU sensor configuration
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal_exynos.h>
|
||||
|
||||
#thermal-sensor-cells = <0>;
|
||||
samsung,tmu_gain = <5>;
|
||||
samsung,tmu_reference_voltage = <16>;
|
||||
samsung,tmu_noise_cancel_mode = <4>;
|
||||
samsung,tmu_efuse_value = <0x5d2d>;
|
||||
samsung,tmu_min_efuse_value = <16>;
|
||||
samsung,tmu_max_efuse_value = <76>;
|
||||
samsung,tmu_first_point_trim = <25>;
|
||||
samsung,tmu_second_point_trim = <70>;
|
||||
samsung,tmu_default_temp_offset = <25>;
|
||||
samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
|
25
arch/arm/boot/dts/exynos5440-trip-points.dtsi
Normal file
25
arch/arm/boot/dts/exynos5440-trip-points.dtsi
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Device tree sources for default Exynos5440 thermal zone definition
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
cpu-alert-0 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu-crit-0 {
|
||||
temperature = <1050000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
@ -219,6 +219,7 @@
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos5440-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmuctrl_1: tmuctrl@16011C {
|
||||
@ -227,6 +228,7 @@
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos5440-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmuctrl_2: tmuctrl@160120 {
|
||||
@ -235,6 +237,22 @@
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos5440-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu0_thermal: cpu0-thermal {
|
||||
thermal-sensors = <&tmuctrl_0>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
cpu1_thermal: cpu1-thermal {
|
||||
thermal-sensors = <&tmuctrl_1>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
cpu2_thermal: cpu2-thermal {
|
||||
thermal-sensors = <&tmuctrl_2>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
sata@210000 {
|
||||
|
@ -35,6 +35,7 @@
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator@1 {
|
||||
@ -45,6 +46,7 @@
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 29 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_audio: regulator@2 {
|
||||
|
@ -52,6 +52,7 @@
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 0 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_usb_otg2_vbus: regulator@1 {
|
||||
@ -62,6 +63,7 @@
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 2 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_aud3v: regulator@2 {
|
||||
|
@ -13,7 +13,7 @@
|
||||
|
||||
core_thermal: core_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 2>;
|
||||
|
@ -13,7 +13,7 @@
|
||||
|
||||
gpu_thermal: gpu_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 1>;
|
||||
|
@ -1079,4 +1079,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
};
|
||||
|
||||
/include/ "omap54xx-clocks.dtsi"
|
||||
|
@ -167,10 +167,18 @@
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_core_byp_mux: dpll_core_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x012c>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-core-clock";
|
||||
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
|
||||
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
|
||||
};
|
||||
|
||||
@ -294,10 +302,18 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_iva_byp_mux: dpll_iva_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x01ac>;
|
||||
};
|
||||
|
||||
dpll_iva_ck: dpll_iva_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
|
||||
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
|
||||
};
|
||||
|
||||
@ -599,10 +615,19 @@
|
||||
};
|
||||
};
|
||||
&cm_core_clocks {
|
||||
|
||||
dpll_per_byp_mux: dpll_per_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x014c>;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
|
||||
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
|
||||
};
|
||||
|
||||
@ -714,10 +739,18 @@
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_usb_byp_mux: dpll_usb_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x018c>;
|
||||
};
|
||||
|
||||
dpll_usb_ck: dpll_usb_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-j-type-clock";
|
||||
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
|
||||
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
|
||||
};
|
||||
|
||||
|
@ -1248,7 +1248,6 @@
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1416,7 +1415,7 @@
|
||||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00700000 0x100000>;
|
||||
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
|
||||
clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -66,6 +66,7 @@
|
||||
gpio4 = &pioE;
|
||||
tcb0 = &tcb0;
|
||||
tcb1 = &tcb1;
|
||||
i2c0 = &i2c0;
|
||||
i2c2 = &i2c2;
|
||||
};
|
||||
cpus {
|
||||
@ -259,7 +260,7 @@
|
||||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00600000 0x100000>;
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
|
||||
clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -461,8 +462,8 @@
|
||||
|
||||
lcdck: lcdck {
|
||||
#clock-cells = <0>;
|
||||
reg = <4>;
|
||||
clocks = <&smd>;
|
||||
reg = <3>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
smdck: smdck {
|
||||
@ -770,7 +771,7 @@
|
||||
reg = <50>;
|
||||
};
|
||||
|
||||
lcd_clk: lcd_clk {
|
||||
lcdc_clk: lcdc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <51>;
|
||||
};
|
||||
|
@ -713,6 +713,9 @@
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
dmas = <&pdma 28>,
|
||||
<&pdma 29>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart1: serial1@ffc03000 {
|
||||
@ -722,6 +725,9 @@
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
dmas = <&pdma 30>,
|
||||
<&pdma 31>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
rst: rstmgr@ffd05000 {
|
||||
|
@ -70,6 +70,7 @@ CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_ARM_AT91_ETHER=y
|
||||
CONFIG_MACB=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
CONFIG_DM9000=y
|
||||
|
@ -99,7 +99,7 @@ CONFIG_PCI_RCAR_GEN2=y
|
||||
CONFIG_PCI_RCAR_GEN2_PCIE=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=8
|
||||
CONFIG_NR_CPUS=16
|
||||
CONFIG_HIGHPTE=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
|
@ -377,6 +377,7 @@ CONFIG_PWM_TWL=m
|
||||
CONFIG_PWM_TWL_LED=m
|
||||
CONFIG_OMAP_USB2=m
|
||||
CONFIG_TI_PIPE3=y
|
||||
CONFIG_TWL4030_USB=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_FS_XATTR is not set
|
||||
|
@ -3,8 +3,6 @@
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
|
@ -4,6 +4,7 @@ CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_ARCH_SUNXI=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=8
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HIGHPTE=y
|
||||
|
@ -118,8 +118,8 @@ CONFIG_HID_ZEROPLUS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_ISP1760_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_ISP1760=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
|
@ -18,8 +18,11 @@
|
||||
#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
|
||||
#endif
|
||||
|
||||
/* Keep in sync with mach-at91/include/mach/hardware.h */
|
||||
#ifdef CONFIG_MMU
|
||||
#define AT91_IO_P2V(x) ((x) - 0x01000000)
|
||||
#else
|
||||
#define AT91_IO_P2V(x) (x)
|
||||
#endif
|
||||
|
||||
#define AT91_DBGU_SR (0x14) /* Status Register */
|
||||
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
|
||||
|
@ -270,37 +270,35 @@ static void __init at91_pm_sram_init(void)
|
||||
phys_addr_t sram_pbase;
|
||||
unsigned long sram_base;
|
||||
struct device_node *node;
|
||||
struct platform_device *pdev;
|
||||
struct platform_device *pdev = NULL;
|
||||
|
||||
node = of_find_compatible_node(NULL, NULL, "mmio-sram");
|
||||
if (!node) {
|
||||
pr_warn("%s: failed to find sram node!\n", __func__);
|
||||
return;
|
||||
for_each_compatible_node(node, NULL, "mmio-sram") {
|
||||
pdev = of_find_device_by_node(node);
|
||||
if (pdev) {
|
||||
of_node_put(node);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pdev = of_find_device_by_node(node);
|
||||
if (!pdev) {
|
||||
pr_warn("%s: failed to find sram device!\n", __func__);
|
||||
goto put_node;
|
||||
return;
|
||||
}
|
||||
|
||||
sram_pool = dev_get_gen_pool(&pdev->dev);
|
||||
if (!sram_pool) {
|
||||
pr_warn("%s: sram pool unavailable!\n", __func__);
|
||||
goto put_node;
|
||||
return;
|
||||
}
|
||||
|
||||
sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
|
||||
if (!sram_base) {
|
||||
pr_warn("%s: unable to alloc ocram!\n", __func__);
|
||||
goto put_node;
|
||||
return;
|
||||
}
|
||||
|
||||
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
|
||||
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
|
||||
|
||||
put_node:
|
||||
of_node_put(node);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -44,7 +44,7 @@ static inline void at91rm9200_standby(void)
|
||||
" mcr p15, 0, %0, c7, c0, 4\n\t"
|
||||
" str %5, [%1, %2]"
|
||||
:
|
||||
: "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
|
||||
: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
|
||||
"r" (1), "r" (AT91RM9200_SDRAMC_SRR),
|
||||
"r" (lpr));
|
||||
}
|
||||
|
@ -25,11 +25,6 @@
|
||||
*/
|
||||
#undef SLOWDOWN_MASTER_CLOCK
|
||||
|
||||
#define MCKRDY_TIMEOUT 1000
|
||||
#define MOSCRDY_TIMEOUT 1000
|
||||
#define PLLALOCK_TIMEOUT 1000
|
||||
#define PLLBLOCK_TIMEOUT 1000
|
||||
|
||||
pmc .req r0
|
||||
sdramc .req r1
|
||||
ramc1 .req r2
|
||||
@ -41,60 +36,42 @@ tmp2 .req r5
|
||||
* Wait until master clock is ready (after switching master clock source)
|
||||
*/
|
||||
.macro wait_mckrdy
|
||||
mov tmp2, #MCKRDY_TIMEOUT
|
||||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MCKRDY
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until master oscillator has stabilized.
|
||||
*/
|
||||
.macro wait_moscrdy
|
||||
mov tmp2, #MOSCRDY_TIMEOUT
|
||||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MOSCS
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until PLLA has locked.
|
||||
*/
|
||||
.macro wait_pllalock
|
||||
mov tmp2, #PLLALOCK_TIMEOUT
|
||||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKA
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until PLLB has locked.
|
||||
*/
|
||||
.macro wait_pllblock
|
||||
mov tmp2, #PLLBLOCK_TIMEOUT
|
||||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKB
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
.arm
|
||||
|
||||
/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
|
||||
* void __iomem *ramc1, int memctrl)
|
||||
*/
|
||||
@ -134,6 +111,16 @@ ddr_sr_enable:
|
||||
cmp memctrl, #AT91_MEMCTRL_DDRSDR
|
||||
bne sdr_sr_enable
|
||||
|
||||
/* LPDDR1 --> force DDR2 mode during self-refresh */
|
||||
ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
|
||||
str tmp1, .saved_sam9_mdr
|
||||
bic tmp1, tmp1, #~AT91_DDRSDRC_MD
|
||||
cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
||||
ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
|
||||
biceq tmp1, tmp1, #AT91_DDRSDRC_MD
|
||||
orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
|
||||
streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
|
||||
|
||||
/* prepare for DDRAM self-refresh mode */
|
||||
ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
str tmp1, .saved_sam9_lpr
|
||||
@ -142,14 +129,26 @@ ddr_sr_enable:
|
||||
|
||||
/* figure out if we use the second ram controller */
|
||||
cmp ramc1, #0
|
||||
ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
strne tmp2, .saved_sam9_lpr1
|
||||
bicne tmp2, #AT91_DDRSDRC_LPCB
|
||||
orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
beq ddr_no_2nd_ctrl
|
||||
|
||||
ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
|
||||
str tmp2, .saved_sam9_mdr1
|
||||
bic tmp2, tmp2, #~AT91_DDRSDRC_MD
|
||||
cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
||||
ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
|
||||
biceq tmp2, tmp2, #AT91_DDRSDRC_MD
|
||||
orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
|
||||
streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
|
||||
|
||||
ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
str tmp2, .saved_sam9_lpr1
|
||||
bic tmp2, #AT91_DDRSDRC_LPCB
|
||||
orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
|
||||
/* Enable DDRAM self-refresh mode */
|
||||
str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
ddr_no_2nd_ctrl:
|
||||
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
|
||||
b sdr_sr_done
|
||||
|
||||
@ -208,6 +207,7 @@ sdr_sr_done:
|
||||
/* Turn off the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
bic tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
orr tmp1, tmp1, #AT91_PMC_KEY
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
/* Wait for interrupt */
|
||||
@ -216,6 +216,7 @@ sdr_sr_done:
|
||||
/* Turn on the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
orr tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
orr tmp1, tmp1, #AT91_PMC_KEY
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
wait_moscrdy
|
||||
@ -280,12 +281,17 @@ sdr_sr_done:
|
||||
*/
|
||||
cmp memctrl, #AT91_MEMCTRL_DDRSDR
|
||||
bne sdr_en_restore
|
||||
/* Restore MDR in case of LPDDR1 */
|
||||
ldr tmp1, .saved_sam9_mdr
|
||||
str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
|
||||
/* Restore LPR on AT91 with DDRAM */
|
||||
ldr tmp1, .saved_sam9_lpr
|
||||
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
|
||||
/* if we use the second ram controller */
|
||||
cmp ramc1, #0
|
||||
ldrne tmp2, .saved_sam9_mdr1
|
||||
strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
|
||||
ldrne tmp2, .saved_sam9_lpr1
|
||||
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
|
||||
@ -319,5 +325,11 @@ ram_restored:
|
||||
.saved_sam9_lpr1:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_mdr:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_mdr1:
|
||||
.word 0
|
||||
|
||||
ENTRY(at91_slow_clock_sz)
|
||||
.word .-at91_slow_clock
|
||||
|
@ -126,8 +126,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
|
||||
*/
|
||||
void exynos_cpu_power_down(int cpu)
|
||||
{
|
||||
if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") ||
|
||||
of_machine_is_compatible("samsung,exynos5800"))) {
|
||||
if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) {
|
||||
/*
|
||||
* Bypass power down for CPU0 during suspend. Check for
|
||||
* the SYS_PWR_REG value to decide if we are suspending
|
||||
|
@ -161,6 +161,34 @@ no_clk:
|
||||
of_genpd_add_provider_simple(np, &pd->pd);
|
||||
}
|
||||
|
||||
/* Assign the child power domains to their parents */
|
||||
for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
|
||||
struct generic_pm_domain *child_domain, *parent_domain;
|
||||
struct of_phandle_args args;
|
||||
|
||||
args.np = np;
|
||||
args.args_count = 0;
|
||||
child_domain = of_genpd_get_from_provider(&args);
|
||||
if (!child_domain)
|
||||
continue;
|
||||
|
||||
if (of_parse_phandle_with_args(np, "power-domains",
|
||||
"#power-domain-cells", 0, &args) != 0)
|
||||
continue;
|
||||
|
||||
parent_domain = of_genpd_get_from_provider(&args);
|
||||
if (!parent_domain)
|
||||
continue;
|
||||
|
||||
if (pm_genpd_add_subdomain(parent_domain, child_domain))
|
||||
pr_warn("%s failed to add subdomain: %s\n",
|
||||
parent_domain->name, child_domain->name);
|
||||
else
|
||||
pr_info("%s has as child subdomain: %s.\n",
|
||||
parent_domain->name, child_domain->name);
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos4_pm_init_power_domain);
|
||||
|
@ -87,8 +87,8 @@ static unsigned int exynos_pmu_spare3;
|
||||
static u32 exynos_irqwake_intmask = 0xffffffff;
|
||||
|
||||
static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
|
||||
{ 73, BIT(1) }, /* RTC alarm */
|
||||
{ 74, BIT(2) }, /* RTC tick */
|
||||
{ 105, BIT(1) }, /* RTC alarm */
|
||||
{ 106, BIT(2) }, /* RTC tick */
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
|
@ -211,8 +211,9 @@ static void __init imx6q_1588_init(void)
|
||||
* set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
|
||||
* (external OSC), and we need to clear the bit.
|
||||
*/
|
||||
clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
|
||||
IMX6Q_GPR1_ENET_CLK_SEL_PAD;
|
||||
clksel = clk_is_match(ptp_clk, enet_ref) ?
|
||||
IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
|
||||
IMX6Q_GPR1_ENET_CLK_SEL_PAD;
|
||||
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
|
||||
if (!IS_ERR(gpr))
|
||||
regmap_update_bits(gpr, IOMUXC_GPR1,
|
||||
|
@ -1692,16 +1692,15 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
|
||||
if (ret == -EBUSY)
|
||||
pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
|
||||
|
||||
if (!ret) {
|
||||
if (oh->clkdm) {
|
||||
/*
|
||||
* Set the clockdomain to HW_AUTO, assuming that the
|
||||
* previous state was HW_AUTO.
|
||||
*/
|
||||
if (oh->clkdm && hwsup)
|
||||
if (hwsup)
|
||||
clkdm_allow_idle(oh->clkdm);
|
||||
} else {
|
||||
if (oh->clkdm)
|
||||
clkdm_hwmod_disable(oh->clkdm, oh);
|
||||
|
||||
clkdm_hwmod_disable(oh->clkdm, oh);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -2698,6 +2697,7 @@ static int __init _register(struct omap_hwmod *oh)
|
||||
INIT_LIST_HEAD(&oh->master_ports);
|
||||
INIT_LIST_HEAD(&oh->slave_ports);
|
||||
spin_lock_init(&oh->_lock);
|
||||
lockdep_set_class(&oh->_lock, &oh->hwmod_key);
|
||||
|
||||
oh->_state = _HWMOD_STATE_REGISTERED;
|
||||
|
||||
|
@ -674,6 +674,7 @@ struct omap_hwmod {
|
||||
u32 _sysc_cache;
|
||||
void __iomem *_mpu_rt_va;
|
||||
spinlock_t _lock;
|
||||
struct lock_class_key hwmod_key; /* unique lock class */
|
||||
struct list_head node;
|
||||
struct omap_hwmod_ocp_if *_mpu_port;
|
||||
unsigned int (*xlate_irq)(unsigned int);
|
||||
|
@ -1466,53 +1466,16 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
|
||||
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
|
||||
.name = "pcie",
|
||||
};
|
||||
|
||||
/* pcie1 */
|
||||
static struct omap_hwmod dra7xx_pcie1_hwmod = {
|
||||
static struct omap_hwmod dra7xx_pciess1_hwmod = {
|
||||
.name = "pcie1",
|
||||
.class = &dra7xx_pcie_hwmod_class,
|
||||
.class = &dra7xx_pciess_hwmod_class,
|
||||
.clkdm_name = "pcie_clkdm",
|
||||
.main_clk = "l4_root_clk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* pcie2 */
|
||||
static struct omap_hwmod dra7xx_pcie2_hwmod = {
|
||||
.name = "pcie2",
|
||||
.class = &dra7xx_pcie_hwmod_class,
|
||||
.clkdm_name = "pcie_clkdm",
|
||||
.main_clk = "l4_root_clk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'PCIE PHY' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
|
||||
.name = "pcie-phy",
|
||||
};
|
||||
|
||||
/* pcie1 phy */
|
||||
static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
|
||||
.name = "pcie1-phy",
|
||||
.class = &dra7xx_pcie_phy_hwmod_class,
|
||||
.clkdm_name = "l3init_clkdm",
|
||||
.main_clk = "l4_root_clk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
|
||||
@ -1522,11 +1485,11 @@ static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
/* pcie2 phy */
|
||||
static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
|
||||
.name = "pcie2-phy",
|
||||
.class = &dra7xx_pcie_phy_hwmod_class,
|
||||
.clkdm_name = "l3init_clkdm",
|
||||
/* pcie2 */
|
||||
static struct omap_hwmod dra7xx_pciess2_hwmod = {
|
||||
.name = "pcie2",
|
||||
.class = &dra7xx_pciess_hwmod_class,
|
||||
.clkdm_name = "pcie_clkdm",
|
||||
.main_clk = "l4_root_clk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -2877,50 +2840,34 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> pcie1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
|
||||
/* l3_main_1 -> pciess1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_pcie1_hwmod,
|
||||
.slave = &dra7xx_pciess1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> pcie1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
|
||||
/* l4_cfg -> pciess1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_pcie1_hwmod,
|
||||
.slave = &dra7xx_pciess1_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> pcie2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
|
||||
/* l3_main_1 -> pciess2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_pcie2_hwmod,
|
||||
.slave = &dra7xx_pciess2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> pcie2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
|
||||
/* l4_cfg -> pciess2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_pcie2_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> pcie1 phy */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_pcie1_phy_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> pcie2 phy */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_pcie2_phy_hwmod,
|
||||
.slave = &dra7xx_pciess2_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
@ -3327,12 +3274,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&dra7xx_l4_cfg__mpu,
|
||||
&dra7xx_l4_cfg__ocp2scp1,
|
||||
&dra7xx_l4_cfg__ocp2scp3,
|
||||
&dra7xx_l3_main_1__pcie1,
|
||||
&dra7xx_l4_cfg__pcie1,
|
||||
&dra7xx_l3_main_1__pcie2,
|
||||
&dra7xx_l4_cfg__pcie2,
|
||||
&dra7xx_l4_cfg__pcie1_phy,
|
||||
&dra7xx_l4_cfg__pcie2_phy,
|
||||
&dra7xx_l3_main_1__pciess1,
|
||||
&dra7xx_l4_cfg__pciess1,
|
||||
&dra7xx_l3_main_1__pciess2,
|
||||
&dra7xx_l4_cfg__pciess2,
|
||||
&dra7xx_l3_main_1__qspi,
|
||||
&dra7xx_l4_per3__rtcss,
|
||||
&dra7xx_l4_cfg__sata,
|
||||
|
@ -173,6 +173,7 @@ static void __init omap3_igep0030_rev_g_legacy_init(void)
|
||||
|
||||
static void __init omap3_evm_legacy_init(void)
|
||||
{
|
||||
hsmmc2_internal_input_clk();
|
||||
legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149);
|
||||
}
|
||||
|
||||
|
@ -252,10 +252,10 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
|
||||
{
|
||||
saved_mask[0] =
|
||||
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
|
||||
OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
OMAP4_PRM_IRQENABLE_MPU_OFFSET);
|
||||
saved_mask[1] =
|
||||
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
|
||||
OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
|
||||
OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
|
||||
|
||||
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
|
||||
OMAP4_PRM_IRQENABLE_MPU_OFFSET);
|
||||
|
@ -36,6 +36,7 @@
|
||||
#include <linux/platform_data/video-pxafb.h>
|
||||
#include <mach/bitfield.h>
|
||||
#include <linux/platform_data/mmc-pxamci.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "devices.h"
|
||||
|
@ -195,7 +195,7 @@ static struct resource smc91x_resources[] = {
|
||||
};
|
||||
|
||||
struct smc91x_platdata smc91x_platdata = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT;
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
|
@ -268,8 +268,8 @@ static int neponset_probe(struct platform_device *dev)
|
||||
.id = 0,
|
||||
.res = smc91x_resources,
|
||||
.num_res = ARRAY_SIZE(smc91x_resources),
|
||||
.data = &smc91c_platdata,
|
||||
.size_data = sizeof(smc91c_platdata),
|
||||
.data = &smc91x_platdata,
|
||||
.size_data = sizeof(smc91x_platdata),
|
||||
};
|
||||
int ret, irq;
|
||||
|
||||
|
@ -54,7 +54,7 @@ static struct platform_device smc91x_device = {
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smc91c_platdata,
|
||||
.platform_data = &smc91x_platdata,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -45,6 +45,6 @@ extern char secondary_trampoline, secondary_trampoline_end;
|
||||
|
||||
extern unsigned long socfpga_cpu1start_addr;
|
||||
|
||||
#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
|
||||
#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
|
||||
|
||||
#endif
|
||||
|
@ -23,6 +23,7 @@
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include "core.h"
|
||||
|
||||
@ -73,6 +74,10 @@ void __init socfpga_sysmgr_init(void)
|
||||
(u32 *) &socfpga_cpu1start_addr))
|
||||
pr_err("SMP: Need cpu1-start-addr in device tree.\n");
|
||||
|
||||
/* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
|
||||
smp_wmb();
|
||||
sync_cache_w(&socfpga_cpu1start_addr);
|
||||
|
||||
sys_manager_base_addr = of_iomap(np, 0);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
|
||||
|
@ -18,6 +18,7 @@ static const char *stih41x_dt_match[] __initdata = {
|
||||
"st,stih415",
|
||||
"st,stih416",
|
||||
"st,stih407",
|
||||
"st,stih410",
|
||||
"st,stih418",
|
||||
NULL
|
||||
};
|
||||
|
@ -622,7 +622,7 @@
|
||||
};
|
||||
|
||||
sgenet0: ethernet@1f210000 {
|
||||
compatible = "apm,xgene-enet";
|
||||
compatible = "apm,xgene1-sgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f210000 0x0 0xd100>,
|
||||
<0x0 0x1f200000 0x0 0Xc300>,
|
||||
@ -636,7 +636,7 @@
|
||||
};
|
||||
|
||||
xgenet: ethernet@1f610000 {
|
||||
compatible = "apm,xgene-enet";
|
||||
compatible = "apm,xgene1-xgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f610000 0x0 0xd100>,
|
||||
<0x0 0x1f600000 0x0 0Xc300>,
|
||||
|
@ -48,6 +48,7 @@ static inline void tlb_flush(struct mmu_gather *tlb)
|
||||
static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
|
||||
unsigned long addr)
|
||||
{
|
||||
__flush_tlb_pgtable(tlb->mm, addr);
|
||||
pgtable_page_dtor(pte);
|
||||
tlb_remove_entry(tlb, pte);
|
||||
}
|
||||
@ -56,6 +57,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
|
||||
static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
|
||||
unsigned long addr)
|
||||
{
|
||||
__flush_tlb_pgtable(tlb->mm, addr);
|
||||
tlb_remove_entry(tlb, virt_to_page(pmdp));
|
||||
}
|
||||
#endif
|
||||
@ -64,6 +66,7 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
|
||||
static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pudp,
|
||||
unsigned long addr)
|
||||
{
|
||||
__flush_tlb_pgtable(tlb->mm, addr);
|
||||
tlb_remove_entry(tlb, virt_to_page(pudp));
|
||||
}
|
||||
#endif
|
||||
|
@ -143,6 +143,19 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
|
||||
flush_tlb_all();
|
||||
}
|
||||
|
||||
/*
|
||||
* Used to invalidate the TLB (walk caches) corresponding to intermediate page
|
||||
* table levels (pgd/pud/pmd).
|
||||
*/
|
||||
static inline void __flush_tlb_pgtable(struct mm_struct *mm,
|
||||
unsigned long uaddr)
|
||||
{
|
||||
unsigned long addr = uaddr >> 12 | ((unsigned long)ASID(mm) << 48);
|
||||
|
||||
dsb(ishst);
|
||||
asm("tlbi vae1is, %0" : : "r" (addr));
|
||||
dsb(ish);
|
||||
}
|
||||
/*
|
||||
* On AArch64, the cache coherency is handled via the set_pte_at() function.
|
||||
*/
|
||||
|
@ -354,3 +354,12 @@ void efi_virtmap_unload(void)
|
||||
efi_set_pgd(current->active_mm);
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
* UpdateCapsule() depends on the system being shutdown via
|
||||
* ResetSystem().
|
||||
*/
|
||||
bool efi_poweroff_required(void)
|
||||
{
|
||||
return efi_enabled(EFI_RUNTIME_SERVICES);
|
||||
}
|
||||
|
@ -585,8 +585,8 @@ ENDPROC(set_cpu_boot_mode_flag)
|
||||
* zeroing of .bss would clobber it.
|
||||
*/
|
||||
.pushsection .data..cacheline_aligned
|
||||
ENTRY(__boot_cpu_mode)
|
||||
.align L1_CACHE_SHIFT
|
||||
ENTRY(__boot_cpu_mode)
|
||||
.long BOOT_CPU_MODE_EL2
|
||||
.long 0
|
||||
.popsection
|
||||
|
@ -21,6 +21,7 @@
|
||||
#include <stdarg.h>
|
||||
|
||||
#include <linux/compat.h>
|
||||
#include <linux/efi.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
@ -150,6 +151,13 @@ void machine_restart(char *cmd)
|
||||
local_irq_disable();
|
||||
smp_send_stop();
|
||||
|
||||
/*
|
||||
* UpdateCapsule() depends on the system being reset via
|
||||
* ResetSystem().
|
||||
*/
|
||||
if (efi_enabled(EFI_RUNTIME_SERVICES))
|
||||
efi_reboot(reboot_mode, NULL);
|
||||
|
||||
/* Now call the architecture specific reboot code. */
|
||||
if (arm_pm_restart)
|
||||
arm_pm_restart(reboot_mode, cmd);
|
||||
|
@ -67,6 +67,11 @@ extern unsigned long empty_zero_page;
|
||||
*/
|
||||
#define pgtable_cache_init() do { } while (0)
|
||||
|
||||
/*
|
||||
* c6x is !MMU, so define the simpliest implementation
|
||||
*/
|
||||
#define pgprot_writecombine pgprot_noncached
|
||||
|
||||
#include <asm-generic/pgtable.h>
|
||||
|
||||
#endif /* _ASM_C6X_PGTABLE_H */
|
||||
|
@ -348,8 +348,9 @@ C_ENTRY(_user_exception):
|
||||
* The LP register should point to the location where the called function
|
||||
* should return. [note that MAKE_SYS_CALL uses label 1] */
|
||||
/* See if the system call number is valid */
|
||||
blti r12, 5f
|
||||
addi r11, r12, -__NR_syscalls;
|
||||
bgei r11,5f;
|
||||
bgei r11, 5f;
|
||||
/* Figure out which function to use for this system call. */
|
||||
/* Note Microblaze barrel shift is optional, so don't rely on it */
|
||||
add r12, r12, r12; /* convert num -> ptr */
|
||||
@ -375,7 +376,7 @@ C_ENTRY(_user_exception):
|
||||
|
||||
/* The syscall number is invalid, return an error. */
|
||||
5:
|
||||
rtsd r15, 8; /* looks like a normal subroutine return */
|
||||
braid ret_from_trap
|
||||
addi r3, r0, -ENOSYS;
|
||||
|
||||
/* Entry point used to return from a syscall/trap */
|
||||
@ -411,7 +412,7 @@ C_ENTRY(ret_from_trap):
|
||||
bri 1b
|
||||
|
||||
/* Maybe handle a signal */
|
||||
5:
|
||||
5:
|
||||
andi r11, r19, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME;
|
||||
beqi r11, 4f; /* Signals to handle, handle them */
|
||||
|
||||
|
@ -15,7 +15,54 @@
|
||||
|
||||
#include <uapi/asm/ptrace.h>
|
||||
|
||||
/* This struct defines the way the registers are stored on the
|
||||
stack during a system call. */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct pt_regs {
|
||||
unsigned long r8; /* r8-r15 Caller-saved GP registers */
|
||||
unsigned long r9;
|
||||
unsigned long r10;
|
||||
unsigned long r11;
|
||||
unsigned long r12;
|
||||
unsigned long r13;
|
||||
unsigned long r14;
|
||||
unsigned long r15;
|
||||
unsigned long r1; /* Assembler temporary */
|
||||
unsigned long r2; /* Retval LS 32bits */
|
||||
unsigned long r3; /* Retval MS 32bits */
|
||||
unsigned long r4; /* r4-r7 Register arguments */
|
||||
unsigned long r5;
|
||||
unsigned long r6;
|
||||
unsigned long r7;
|
||||
unsigned long orig_r2; /* Copy of r2 ?? */
|
||||
unsigned long ra; /* Return address */
|
||||
unsigned long fp; /* Frame pointer */
|
||||
unsigned long sp; /* Stack pointer */
|
||||
unsigned long gp; /* Global pointer */
|
||||
unsigned long estatus;
|
||||
unsigned long ea; /* Exception return address (pc) */
|
||||
unsigned long orig_r7;
|
||||
};
|
||||
|
||||
/*
|
||||
* This is the extended stack used by signal handlers and the context
|
||||
* switcher: it's pushed after the normal "struct pt_regs".
|
||||
*/
|
||||
struct switch_stack {
|
||||
unsigned long r16; /* r16-r23 Callee-saved GP registers */
|
||||
unsigned long r17;
|
||||
unsigned long r18;
|
||||
unsigned long r19;
|
||||
unsigned long r20;
|
||||
unsigned long r21;
|
||||
unsigned long r22;
|
||||
unsigned long r23;
|
||||
unsigned long fp;
|
||||
unsigned long gp;
|
||||
unsigned long ra;
|
||||
};
|
||||
|
||||
#define user_mode(regs) (((regs)->estatus & ESTATUS_EU))
|
||||
|
||||
#define instruction_pointer(regs) ((regs)->ra)
|
||||
|
@ -1,32 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
|
||||
* Copyright (C) 2004 Microtronix Datacom Ltd
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_NIOS2_UCONTEXT_H
|
||||
#define _ASM_NIOS2_UCONTEXT_H
|
||||
|
||||
typedef int greg_t;
|
||||
#define NGREG 32
|
||||
typedef greg_t gregset_t[NGREG];
|
||||
|
||||
struct mcontext {
|
||||
int version;
|
||||
gregset_t gregs;
|
||||
};
|
||||
|
||||
#define MCONTEXT_VERSION 2
|
||||
|
||||
struct ucontext {
|
||||
unsigned long uc_flags;
|
||||
struct ucontext *uc_link;
|
||||
stack_t uc_stack;
|
||||
struct mcontext uc_mcontext;
|
||||
sigset_t uc_sigmask; /* mask last for extensibility */
|
||||
};
|
||||
|
||||
#endif
|
@ -2,3 +2,5 @@ include include/uapi/asm-generic/Kbuild.asm
|
||||
|
||||
header-y += elf.h
|
||||
header-y += ucontext.h
|
||||
|
||||
generic-y += ucontext.h
|
||||
|
@ -50,9 +50,7 @@
|
||||
|
||||
typedef unsigned long elf_greg_t;
|
||||
|
||||
#define ELF_NGREG \
|
||||
((sizeof(struct pt_regs) + sizeof(struct switch_stack)) / \
|
||||
sizeof(elf_greg_t))
|
||||
#define ELF_NGREG 49
|
||||
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
|
||||
|
||||
typedef unsigned long elf_fpregset_t;
|
||||
|
@ -67,53 +67,9 @@
|
||||
|
||||
#define NUM_PTRACE_REG (PTR_TLBMISC + 1)
|
||||
|
||||
/* this struct defines the way the registers are stored on the
|
||||
stack during a system call.
|
||||
|
||||
There is a fake_regs in setup.c that has to match pt_regs.*/
|
||||
|
||||
struct pt_regs {
|
||||
unsigned long r8; /* r8-r15 Caller-saved GP registers */
|
||||
unsigned long r9;
|
||||
unsigned long r10;
|
||||
unsigned long r11;
|
||||
unsigned long r12;
|
||||
unsigned long r13;
|
||||
unsigned long r14;
|
||||
unsigned long r15;
|
||||
unsigned long r1; /* Assembler temporary */
|
||||
unsigned long r2; /* Retval LS 32bits */
|
||||
unsigned long r3; /* Retval MS 32bits */
|
||||
unsigned long r4; /* r4-r7 Register arguments */
|
||||
unsigned long r5;
|
||||
unsigned long r6;
|
||||
unsigned long r7;
|
||||
unsigned long orig_r2; /* Copy of r2 ?? */
|
||||
unsigned long ra; /* Return address */
|
||||
unsigned long fp; /* Frame pointer */
|
||||
unsigned long sp; /* Stack pointer */
|
||||
unsigned long gp; /* Global pointer */
|
||||
unsigned long estatus;
|
||||
unsigned long ea; /* Exception return address (pc) */
|
||||
unsigned long orig_r7;
|
||||
};
|
||||
|
||||
/*
|
||||
* This is the extended stack used by signal handlers and the context
|
||||
* switcher: it's pushed after the normal "struct pt_regs".
|
||||
*/
|
||||
struct switch_stack {
|
||||
unsigned long r16; /* r16-r23 Callee-saved GP registers */
|
||||
unsigned long r17;
|
||||
unsigned long r18;
|
||||
unsigned long r19;
|
||||
unsigned long r20;
|
||||
unsigned long r21;
|
||||
unsigned long r22;
|
||||
unsigned long r23;
|
||||
unsigned long fp;
|
||||
unsigned long gp;
|
||||
unsigned long ra;
|
||||
/* User structures for general purpose registers. */
|
||||
struct user_pt_regs {
|
||||
__u32 regs[49];
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
@ -15,14 +15,16 @@
|
||||
* details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_NIOS2_SIGCONTEXT_H
|
||||
#define _ASM_NIOS2_SIGCONTEXT_H
|
||||
#ifndef _UAPI__ASM_SIGCONTEXT_H
|
||||
#define _UAPI__ASM_SIGCONTEXT_H
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define MCONTEXT_VERSION 2
|
||||
|
||||
struct sigcontext {
|
||||
struct pt_regs regs;
|
||||
unsigned long sc_mask; /* old sigmask */
|
||||
int version;
|
||||
unsigned long gregs[32];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
@ -39,7 +39,7 @@ static inline int rt_restore_ucontext(struct pt_regs *regs,
|
||||
struct ucontext *uc, int *pr2)
|
||||
{
|
||||
int temp;
|
||||
greg_t *gregs = uc->uc_mcontext.gregs;
|
||||
unsigned long *gregs = uc->uc_mcontext.gregs;
|
||||
int err;
|
||||
|
||||
/* Always make any pending restarted system calls return -EINTR */
|
||||
@ -127,7 +127,7 @@ badframe:
|
||||
static inline int rt_setup_ucontext(struct ucontext *uc, struct pt_regs *regs)
|
||||
{
|
||||
struct switch_stack *sw = (struct switch_stack *)regs - 1;
|
||||
greg_t *gregs = uc->uc_mcontext.gregs;
|
||||
unsigned long *gregs = uc->uc_mcontext.gregs;
|
||||
int err = 0;
|
||||
|
||||
err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
|
||||
|
@ -515,15 +515,15 @@ struct s390_io_adapter {
|
||||
#define S390_ARCH_FAC_MASK_SIZE_U64 \
|
||||
(S390_ARCH_FAC_MASK_SIZE_BYTE / sizeof(u64))
|
||||
|
||||
struct s390_model_fac {
|
||||
/* facilities used in SIE context */
|
||||
__u64 sie[S390_ARCH_FAC_LIST_SIZE_U64];
|
||||
/* subset enabled by kvm */
|
||||
__u64 kvm[S390_ARCH_FAC_LIST_SIZE_U64];
|
||||
struct kvm_s390_fac {
|
||||
/* facility list requested by guest */
|
||||
__u64 list[S390_ARCH_FAC_LIST_SIZE_U64];
|
||||
/* facility mask supported by kvm & hosting machine */
|
||||
__u64 mask[S390_ARCH_FAC_LIST_SIZE_U64];
|
||||
};
|
||||
|
||||
struct kvm_s390_cpu_model {
|
||||
struct s390_model_fac *fac;
|
||||
struct kvm_s390_fac *fac;
|
||||
struct cpuid cpu_id;
|
||||
unsigned short ibc;
|
||||
};
|
||||
|
@ -62,6 +62,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
S390_lowcore.user_asce = next->context.asce_bits | __pa(next->pgd);
|
||||
if (prev == next)
|
||||
return;
|
||||
if (MACHINE_HAS_TLB_LC)
|
||||
@ -73,7 +74,6 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
atomic_dec(&prev->context.attach_count);
|
||||
if (MACHINE_HAS_TLB_LC)
|
||||
cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
|
||||
S390_lowcore.user_asce = next->context.asce_bits | __pa(next->pgd);
|
||||
}
|
||||
|
||||
#define finish_arch_post_lock_switch finish_arch_post_lock_switch
|
||||
|
@ -37,16 +37,7 @@ static inline void storage_key_init_range(unsigned long start, unsigned long end
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void clear_page(void *page)
|
||||
{
|
||||
register unsigned long reg1 asm ("1") = 0;
|
||||
register void *reg2 asm ("2") = page;
|
||||
register unsigned long reg3 asm ("3") = 4096;
|
||||
asm volatile(
|
||||
" mvcl 2,0"
|
||||
: "+d" (reg2), "+d" (reg3) : "d" (reg1)
|
||||
: "memory", "cc");
|
||||
}
|
||||
#define clear_page(page) memset((page), 0, PAGE_SIZE)
|
||||
|
||||
/*
|
||||
* copy_page uses the mvcl instruction with 0xb0 padding byte in order to
|
||||
|
@ -36,16 +36,20 @@ static void jump_label_make_branch(struct jump_entry *entry, struct insn *insn)
|
||||
insn->offset = (entry->target - entry->code) >> 1;
|
||||
}
|
||||
|
||||
static void jump_label_bug(struct jump_entry *entry, struct insn *insn)
|
||||
static void jump_label_bug(struct jump_entry *entry, struct insn *expected,
|
||||
struct insn *new)
|
||||
{
|
||||
unsigned char *ipc = (unsigned char *)entry->code;
|
||||
unsigned char *ipe = (unsigned char *)insn;
|
||||
unsigned char *ipe = (unsigned char *)expected;
|
||||
unsigned char *ipn = (unsigned char *)new;
|
||||
|
||||
pr_emerg("Jump label code mismatch at %pS [%p]\n", ipc, ipc);
|
||||
pr_emerg("Found: %02x %02x %02x %02x %02x %02x\n",
|
||||
ipc[0], ipc[1], ipc[2], ipc[3], ipc[4], ipc[5]);
|
||||
pr_emerg("Expected: %02x %02x %02x %02x %02x %02x\n",
|
||||
ipe[0], ipe[1], ipe[2], ipe[3], ipe[4], ipe[5]);
|
||||
pr_emerg("New: %02x %02x %02x %02x %02x %02x\n",
|
||||
ipn[0], ipn[1], ipn[2], ipn[3], ipn[4], ipn[5]);
|
||||
panic("Corrupted kernel text");
|
||||
}
|
||||
|
||||
@ -69,10 +73,10 @@ static void __jump_label_transform(struct jump_entry *entry,
|
||||
}
|
||||
if (init) {
|
||||
if (memcmp((void *)entry->code, &orignop, sizeof(orignop)))
|
||||
jump_label_bug(entry, &old);
|
||||
jump_label_bug(entry, &orignop, &new);
|
||||
} else {
|
||||
if (memcmp((void *)entry->code, &old, sizeof(old)))
|
||||
jump_label_bug(entry, &old);
|
||||
jump_label_bug(entry, &old, &new);
|
||||
}
|
||||
probe_kernel_write((void *)entry->code, &new, sizeof(new));
|
||||
}
|
||||
|
@ -436,6 +436,7 @@ int module_finalize(const Elf_Ehdr *hdr,
|
||||
const Elf_Shdr *sechdrs,
|
||||
struct module *me)
|
||||
{
|
||||
jump_label_apply_nops(me);
|
||||
vfree(me->arch.syminfo);
|
||||
me->arch.syminfo = NULL;
|
||||
return 0;
|
||||
|
@ -18,7 +18,7 @@
|
||||
|
||||
static DEFINE_PER_CPU(struct cpuid, cpu_id);
|
||||
|
||||
void cpu_relax(void)
|
||||
void notrace cpu_relax(void)
|
||||
{
|
||||
if (!smp_cpu_mtid && MACHINE_HAS_DIAG44)
|
||||
asm volatile("diag 0,0,0x44");
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user