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dt-bindings: interconnect: Add bindings for Qualcomm SDM660 NoC
Add the bindings for the Qualcomm SDM660-class NoC, valid for SDM630, SDM636, SDM660 and SDA variants. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201017133718.31327-2-kholk11@gmail.com Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
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Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDM660 Network-On-Chip interconnect
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maintainers:
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- AngeloGioacchino Del Regno <kholk11@gmail.com>
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description: |
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The Qualcomm SDM660 interconnect providers support adjusting the
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bandwidth requirements between the various NoC fabrics.
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properties:
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reg:
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maxItems: 1
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compatible:
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enum:
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- qcom,sdm660-a2noc
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- qcom,sdm660-bimc
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- qcom,sdm660-cnoc
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- qcom,sdm660-gnoc
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- qcom,sdm660-mnoc
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- qcom,sdm660-snoc
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'#interconnect-cells':
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const: 1
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clocks:
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minItems: 1
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maxItems: 3
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clock-names:
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minItems: 1
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maxItems: 3
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required:
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- compatible
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- reg
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- '#interconnect-cells'
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- clock-names
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- clocks
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdm660-mnoc
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then:
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properties:
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clocks:
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items:
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- description: Bus Clock.
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- description: Bus A Clock.
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- description: CPU-NoC High-performance Bus Clock.
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clock-names:
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items:
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- const: bus
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- const: bus_a
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- const: iface
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdm660-a2noc
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- qcom,sdm660-bimc
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- qcom,sdm660-cnoc
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- qcom,sdm660-gnoc
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- qcom,sdm660-snoc
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then:
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properties:
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clocks:
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items:
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- description: Bus Clock.
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- description: Bus A Clock.
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clock-names:
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items:
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- const: bus
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- const: bus_a
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
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bimc: interconnect@1008000 {
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compatible = "qcom,sdm660-bimc";
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reg = <0x01008000 0x78000>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
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<&rpmcc RPM_SMD_BIMC_A_CLK>;
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};
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cnoc: interconnect@1500000 {
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compatible = "qcom,sdm660-cnoc";
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reg = <0x01500000 0x10000>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
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<&rpmcc RPM_SMD_CNOC_A_CLK>;
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};
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snoc: interconnect@1626000 {
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compatible = "qcom,sdm660-snoc";
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reg = <0x01626000 0x7090>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
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<&rpmcc RPM_SMD_SNOC_A_CLK>;
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};
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a2noc: interconnect@1704000 {
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compatible = "qcom,sdm660-a2noc";
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reg = <0x01704000 0xc100>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
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<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
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};
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mnoc: interconnect@1745000 {
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compatible = "qcom,sdm660-mnoc";
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reg = <0x01745000 0xa010>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a", "iface";
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clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
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<&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
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<&mmcc AHB_CLK_SRC>;
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};
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gnoc: interconnect@17900000 {
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compatible = "qcom,sdm660-gnoc";
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reg = <0x17900000 0xe000>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&xo_board>, <&xo_board>;
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};
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include/dt-bindings/interconnect/qcom,sdm660.h
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include/dt-bindings/interconnect/qcom,sdm660.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/* SDM660 interconnect IDs */
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H
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/* A2NOC */
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#define MASTER_IPA 0
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#define MASTER_CNOC_A2NOC 1
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#define MASTER_SDCC_1 2
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#define MASTER_SDCC_2 3
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#define MASTER_BLSP_1 4
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#define MASTER_BLSP_2 5
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#define MASTER_UFS 6
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#define MASTER_USB_HS 7
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#define MASTER_USB3 8
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#define MASTER_CRYPTO_C0 9
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#define SLAVE_A2NOC_SNOC 10
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/* BIMC */
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#define MASTER_GNOC_BIMC 0
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#define MASTER_OXILI 1
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#define MASTER_MNOC_BIMC 2
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#define MASTER_SNOC_BIMC 3
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#define MASTER_PIMEM 4
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#define SLAVE_EBI 5
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#define SLAVE_HMSS_L3 6
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#define SLAVE_BIMC_SNOC 7
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/* CNOC */
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#define MASTER_SNOC_CNOC 0
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#define MASTER_QDSS_DAP 1
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#define SLAVE_CNOC_A2NOC 2
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#define SLAVE_MPM 3
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#define SLAVE_PMIC_ARB 4
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#define SLAVE_TLMM_NORTH 5
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#define SLAVE_TCSR 6
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#define SLAVE_PIMEM_CFG 7
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#define SLAVE_IMEM_CFG 8
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#define SLAVE_MESSAGE_RAM 9
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#define SLAVE_GLM 10
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#define SLAVE_BIMC_CFG 11
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#define SLAVE_PRNG 12
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#define SLAVE_SPDM 13
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#define SLAVE_QDSS_CFG 14
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#define SLAVE_CNOC_MNOC_CFG 15
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#define SLAVE_SNOC_CFG 16
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#define SLAVE_QM_CFG 17
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#define SLAVE_CLK_CTL 18
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#define SLAVE_MSS_CFG 19
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#define SLAVE_TLMM_SOUTH 20
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#define SLAVE_UFS_CFG 21
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#define SLAVE_A2NOC_CFG 22
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#define SLAVE_A2NOC_SMMU_CFG 23
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#define SLAVE_GPUSS_CFG 24
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#define SLAVE_AHB2PHY 25
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#define SLAVE_BLSP_1 26
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#define SLAVE_SDCC_1 27
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#define SLAVE_SDCC_2 28
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#define SLAVE_TLMM_CENTER 29
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#define SLAVE_BLSP_2 30
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#define SLAVE_PDM 31
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#define SLAVE_CNOC_MNOC_MMSS_CFG 32
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#define SLAVE_USB_HS 33
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#define SLAVE_USB3_0 34
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#define SLAVE_SRVC_CNOC 35
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/* GNOC */
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#define MASTER_APSS_PROC 0
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#define SLAVE_GNOC_BIMC 1
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#define SLAVE_GNOC_SNOC 2
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/* MNOC */
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#define MASTER_CPP 0
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#define MASTER_JPEG 1
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#define MASTER_MDP_P0 2
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#define MASTER_MDP_P1 3
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#define MASTER_VENUS 4
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#define MASTER_VFE 5
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#define SLAVE_MNOC_BIMC 6
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#define MASTER_CNOC_MNOC_MMSS_CFG 7
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#define MASTER_CNOC_MNOC_CFG 8
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#define SLAVE_CAMERA_CFG 9
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#define SLAVE_CAMERA_THROTTLE_CFG 10
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#define SLAVE_MISC_CFG 11
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#define SLAVE_VENUS_THROTTLE_CFG 12
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#define SLAVE_VENUS_CFG 13
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#define SLAVE_MMSS_CLK_XPU_CFG 14
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#define SLAVE_MMSS_CLK_CFG 15
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#define SLAVE_MNOC_MPU_CFG 16
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#define SLAVE_DISPLAY_CFG 17
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#define SLAVE_CSI_PHY_CFG 18
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#define SLAVE_DISPLAY_THROTTLE_CFG 19
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#define SLAVE_SMMU_CFG 20
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#define SLAVE_SRVC_MNOC 21
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/* SNOC */
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#define MASTER_QDSS_ETR 0
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#define MASTER_QDSS_BAM 1
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#define MASTER_SNOC_CFG 2
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#define MASTER_BIMC_SNOC 3
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#define MASTER_A2NOC_SNOC 4
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#define MASTER_GNOC_SNOC 5
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#define SLAVE_HMSS 6
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#define SLAVE_LPASS 7
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#define SLAVE_WLAN 8
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#define SLAVE_CDSP 9
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#define SLAVE_IPA 10
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#define SLAVE_SNOC_BIMC 11
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#define SLAVE_SNOC_CNOC 12
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#define SLAVE_IMEM 13
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#define SLAVE_PIMEM 14
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#define SLAVE_QDSS_STM 15
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#define SLAVE_SRVC_SNOC 16
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#endif
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