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drm/tegra: dc: Implement runtime PM
Use runtime PM to clock-gate, assert reset and powergate the display controller. This ties in nicely with atomic DPMS in that a runtime PM reference is taken before a pipe is enabled and dropped after it has been shut down. To make sure this works, make sure to only ever update planes on active CRTCs, otherwise register accesses to a clock-gated and reset CRTC will hang the CPU. Signed-off-by: Thierry Reding <treding@nvidia.com>
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2ccb396e9d
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@ -10,6 +10,7 @@
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/iommu.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <soc/tegra/pmc.h>
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@ -1216,6 +1217,8 @@ static void tegra_crtc_disable(struct drm_crtc *crtc)
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tegra_dc_stats_reset(&dc->stats);
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drm_crtc_vblank_off(crtc);
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pm_runtime_put_sync(dc->dev);
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}
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static void tegra_crtc_enable(struct drm_crtc *crtc)
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@ -1225,6 +1228,48 @@ static void tegra_crtc_enable(struct drm_crtc *crtc)
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struct tegra_dc *dc = to_tegra_dc(crtc);
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u32 value;
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pm_runtime_get_sync(dc->dev);
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/* initialize display controller */
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if (dc->syncpt) {
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u32 syncpt = host1x_syncpt_id(dc->syncpt);
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value = SYNCPT_CNTRL_NO_STALL;
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tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
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value = SYNCPT_VSYNC_ENABLE | syncpt;
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tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
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}
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
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/* initialize timer */
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
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WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
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WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
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value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
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if (dc->soc->supports_border_color)
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tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
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/* apply PLL and pixel clock changes */
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tegra_dc_commit_state(dc, state);
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/* program display mode */
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@ -1685,7 +1730,6 @@ static int tegra_dc_init(struct host1x_client *client)
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struct tegra_drm *tegra = drm->dev_private;
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struct drm_plane *primary = NULL;
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struct drm_plane *cursor = NULL;
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u32 value;
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int err;
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dc->syncpt = host1x_syncpt_request(dc->dev, flags);
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@ -1755,47 +1799,6 @@ static int tegra_dc_init(struct host1x_client *client)
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goto cleanup;
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}
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/* initialize display controller */
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if (dc->syncpt) {
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u32 syncpt = host1x_syncpt_id(dc->syncpt);
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value = SYNCPT_CNTRL_NO_STALL;
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tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
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value = SYNCPT_VSYNC_ENABLE | syncpt;
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tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
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}
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
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/* initialize timer */
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
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WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
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WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
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value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
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if (dc->soc->supports_border_color)
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tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
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tegra_dc_stats_reset(&dc->stats);
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return 0;
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cleanup:
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@ -1987,33 +1990,15 @@ static int tegra_dc_probe(struct platform_device *pdev)
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return PTR_ERR(dc->rst);
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}
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reset_control_assert(dc->rst);
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if (dc->soc->has_powergate) {
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if (dc->pipe == 0)
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dc->powergate = TEGRA_POWERGATE_DIS;
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else
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dc->powergate = TEGRA_POWERGATE_DISB;
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err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
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dc->rst);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to power partition: %d\n",
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err);
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return err;
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}
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} else {
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err = clk_prepare_enable(dc->clk);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to enable clock: %d\n",
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err);
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return err;
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}
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err = reset_control_deassert(dc->rst);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to deassert reset: %d\n",
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err);
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return err;
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}
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tegra_powergate_power_off(dc->powergate);
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}
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -2027,16 +2012,19 @@ static int tegra_dc_probe(struct platform_device *pdev)
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return -ENXIO;
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}
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INIT_LIST_HEAD(&dc->client.list);
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dc->client.ops = &dc_client_ops;
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dc->client.dev = &pdev->dev;
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err = tegra_dc_rgb_probe(dc);
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if (err < 0 && err != -ENODEV) {
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dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
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return err;
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}
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platform_set_drvdata(pdev, dc);
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pm_runtime_enable(&pdev->dev);
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INIT_LIST_HEAD(&dc->client.list);
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dc->client.ops = &dc_client_ops;
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dc->client.dev = &pdev->dev;
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err = host1x_client_register(&dc->client);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to register host1x client: %d\n",
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@ -2044,8 +2032,6 @@ static int tegra_dc_probe(struct platform_device *pdev)
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return err;
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}
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platform_set_drvdata(pdev, dc);
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return 0;
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}
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@ -2067,7 +2053,22 @@ static int tegra_dc_remove(struct platform_device *pdev)
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return err;
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}
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reset_control_assert(dc->rst);
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int tegra_dc_suspend(struct device *dev)
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{
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struct tegra_dc *dc = dev_get_drvdata(dev);
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int err;
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err = reset_control_assert(dc->rst);
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if (err < 0) {
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dev_err(dev, "failed to assert reset: %d\n", err);
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return err;
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}
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if (dc->soc->has_powergate)
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tegra_powergate_power_off(dc->powergate);
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@ -2077,10 +2078,45 @@ static int tegra_dc_remove(struct platform_device *pdev)
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return 0;
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}
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static int tegra_dc_resume(struct device *dev)
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{
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struct tegra_dc *dc = dev_get_drvdata(dev);
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int err;
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if (dc->soc->has_powergate) {
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err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
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dc->rst);
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if (err < 0) {
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dev_err(dev, "failed to power partition: %d\n", err);
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return err;
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}
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} else {
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err = clk_prepare_enable(dc->clk);
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if (err < 0) {
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dev_err(dev, "failed to enable clock: %d\n", err);
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return err;
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}
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err = reset_control_deassert(dc->rst);
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if (err < 0) {
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dev_err(dev, "failed to deassert reset: %d\n", err);
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return err;
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}
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}
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return 0;
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}
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#endif
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static const struct dev_pm_ops tegra_dc_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
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};
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struct platform_driver tegra_dc_driver = {
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.driver = {
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.name = "tegra-dc",
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.of_match_table = tegra_dc_of_match,
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.pm = &tegra_dc_pm_ops,
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},
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.probe = tegra_dc_probe,
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.remove = tegra_dc_remove,
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@ -56,8 +56,8 @@ static void tegra_atomic_complete(struct tegra_drm *tegra,
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*/
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drm_atomic_helper_commit_modeset_disables(drm, state);
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drm_atomic_helper_commit_planes(drm, state, false);
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drm_atomic_helper_commit_modeset_enables(drm, state);
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drm_atomic_helper_commit_planes(drm, state, true);
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drm_atomic_helper_wait_for_vblanks(drm, state);
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