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drm/meson: Add support for HDMI venc modes and settings
This patch adds support for the supported HDMI Venc modes and add the VPP mux value to switch to ENCP encoder. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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@ -30,6 +30,7 @@ enum {
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MESON_VENC_MODE_NONE = 0,
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MESON_VENC_MODE_CVBS_PAL,
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MESON_VENC_MODE_CVBS_NTSC,
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MESON_VENC_MODE_HDMI,
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};
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struct meson_cvbs_enci_mode {
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@ -56,12 +57,18 @@ struct meson_cvbs_enci_mode {
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unsigned int analog_sync_adj;
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};
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/* HDMI Clock parameters */
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bool meson_venc_hdmi_supported_vic(int vic);
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bool meson_venc_hdmi_venc_repeat(int vic);
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/* CVBS Timings and Parameters */
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extern struct meson_cvbs_enci_mode meson_cvbs_enci_pal;
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extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc;
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void meson_venci_cvbs_mode_set(struct meson_drm *priv,
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struct meson_cvbs_enci_mode *mode);
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void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
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struct drm_display_mode *mode);
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unsigned int meson_venci_get_field(struct meson_drm *priv);
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void meson_venc_enable_vsync(struct meson_drm *priv);
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@ -23,6 +23,8 @@
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/* Mux VIU/VPP to ENCI */
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#define MESON_VIU_VPP_MUX_ENCI 0x5
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/* Mux VIU/VPP to ENCP */
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#define MESON_VIU_VPP_MUX_ENCP 0xA
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void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux);
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