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intel_idle: export both C1 and C1E
Here we disable HW promotion of C1 to C1E and export both C1 and C1E and distinct C-states. This allows a cpuidle governor to choose a lower latency C-state than C1E when necessary to satisfy performance and QOS constraints -- and still save power versus polling. This also corrects the erroneous latency previously reported for C1E -- it is 10usec, not 1usec. Note that if you use "intel_idle.max_cstate=N", then you must increment N by 1 to get the same behavior after this change. Signed-off-by: Len Brown <len.brown@intel.com>
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@ -90,6 +90,7 @@ struct idle_cpu {
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* Indicate which enable bits to clear here.
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*/
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unsigned long auto_demotion_disable_flags;
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bool disable_promotion_to_c1e;
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};
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static const struct idle_cpu *icpu;
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@ -131,6 +132,13 @@ static struct cpuidle_state nehalem_cstates[CPUIDLE_STATE_MAX] = {
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.exit_latency = 3,
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.target_residency = 6,
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.enter = &intel_idle },
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{
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.name = "C1E-NHM",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C3-NHM",
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.desc = "MWAIT 0x10",
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@ -154,8 +162,15 @@ static struct cpuidle_state snb_cstates[CPUIDLE_STATE_MAX] = {
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.name = "C1-SNB",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 1,
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.target_residency = 1,
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle },
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{
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.name = "C1E-SNB",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C3-SNB",
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@ -190,6 +205,13 @@ static struct cpuidle_state ivb_cstates[CPUIDLE_STATE_MAX] = {
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle },
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{
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.name = "C1E-IVB",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C3-IVB",
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.desc = "MWAIT 0x10",
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@ -223,6 +245,13 @@ static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = {
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle },
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{
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.name = "C1E-HSW",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C3-HSW",
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.desc = "MWAIT 0x10",
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@ -250,11 +279,11 @@ static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = {
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static struct cpuidle_state atom_cstates[CPUIDLE_STATE_MAX] = {
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{
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.name = "C1-ATM",
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.name = "C1E-ATM",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 1,
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.target_residency = 4,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C2-ATM",
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@ -377,10 +406,19 @@ static void auto_demotion_disable(void *dummy)
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msr_bits &= ~(icpu->auto_demotion_disable_flags);
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wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
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}
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static void c1e_promotion_disable(void *dummy)
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{
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unsigned long long msr_bits;
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rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
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msr_bits &= ~0x2;
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wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
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}
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static const struct idle_cpu idle_cpu_nehalem = {
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.state_table = nehalem_cstates,
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.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
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.disable_promotion_to_c1e = true,
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};
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static const struct idle_cpu idle_cpu_atom = {
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@ -394,14 +432,17 @@ static const struct idle_cpu idle_cpu_lincroft = {
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static const struct idle_cpu idle_cpu_snb = {
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.state_table = snb_cstates,
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.disable_promotion_to_c1e = true,
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};
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static const struct idle_cpu idle_cpu_ivb = {
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.state_table = ivb_cstates,
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.disable_promotion_to_c1e = true,
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};
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static const struct idle_cpu idle_cpu_hsw = {
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.state_table = hsw_cstates,
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.disable_promotion_to_c1e = true,
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};
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#define ICPU(model, cpu) \
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@ -544,6 +585,9 @@ static int intel_idle_cpuidle_driver_init(void)
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if (icpu->auto_demotion_disable_flags)
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on_each_cpu(auto_demotion_disable, NULL, 1);
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if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */
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on_each_cpu(c1e_promotion_disable, NULL, 1);
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return 0;
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}
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