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mtd: spi-nor: Fix address width on flash chips > 16MB
If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_set_addr_width() doesn't catch it because addr_width
did get set. This fixes that check.
Fixes: f9acd7fa80
("mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths")
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Joel Stanley <joel@jms.id.au>
Tested-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20201006132346.12652-1-bert@biot.com
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@ -3008,13 +3008,15 @@ static int spi_nor_set_addr_width(struct spi_nor *nor)
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/* already configured from SFDP */
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} else if (nor->info->addr_width) {
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nor->addr_width = nor->info->addr_width;
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} else if (nor->mtd.size > 0x1000000) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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} else {
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nor->addr_width = 3;
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}
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if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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}
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if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
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dev_dbg(nor->dev, "address width is too large: %u\n",
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nor->addr_width);
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