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drm/radeon: rework finding display PLL numbers v2
This completely reworks how the PLL parameters are generated and should result in better matching dot clock frequencies. Probably needs quite a bit of testing. bugs: https://bugs.freedesktop.org/show_bug.cgi?id=76564 v2: more cleanup and comments. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
parent
ec9954fc26
commit
3216701607
@ -34,6 +34,8 @@
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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#include <linux/gcd.h>
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static void avivo_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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@ -799,66 +801,57 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
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}
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/* avivo */
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static void avivo_get_fb_div(struct radeon_pll *pll,
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u32 target_clock,
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u32 post_div,
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u32 ref_div,
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u32 *fb_div,
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u32 *frac_fb_div)
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/**
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* avivo_reduce_ratio - fractional number reduction
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*
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* @nom: nominator
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* @den: denominator
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* @nom_min: minimum value for nominator
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* @den_min: minimum value for denominator
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*
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* Find the greatest common divisor and apply it on both nominator and
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* denominator, but make nominator and denominator are at least as large
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* as their minimum values.
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*/
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static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
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unsigned nom_min, unsigned den_min)
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{
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u32 tmp = post_div * ref_div;
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unsigned tmp;
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tmp *= target_clock;
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*fb_div = tmp / pll->reference_freq;
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*frac_fb_div = tmp % pll->reference_freq;
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/* reduce the numbers to a simpler ratio */
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tmp = gcd(*nom, *den);
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*nom /= tmp;
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*den /= tmp;
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if (*fb_div > pll->max_feedback_div)
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*fb_div = pll->max_feedback_div;
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else if (*fb_div < pll->min_feedback_div)
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*fb_div = pll->min_feedback_div;
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}
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static u32 avivo_get_post_div(struct radeon_pll *pll,
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u32 target_clock)
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{
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u32 vco, post_div, tmp;
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if (pll->flags & RADEON_PLL_USE_POST_DIV)
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return pll->post_div;
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if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
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if (pll->flags & RADEON_PLL_IS_LCD)
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vco = pll->lcd_pll_out_min;
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else
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vco = pll->pll_out_min;
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} else {
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if (pll->flags & RADEON_PLL_IS_LCD)
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vco = pll->lcd_pll_out_max;
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else
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vco = pll->pll_out_max;
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/* make sure nominator is large enough */
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if (*nom < nom_min) {
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tmp = (nom_min + *nom - 1) / *nom;
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*nom *= tmp;
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*den *= tmp;
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}
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post_div = vco / target_clock;
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tmp = vco % target_clock;
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if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
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if (tmp)
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post_div++;
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} else {
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if (!tmp)
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post_div--;
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/* make sure the denominator is large enough */
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if (*den < den_min) {
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tmp = (den_min + *den - 1) / *den;
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*nom *= tmp;
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*den *= tmp;
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}
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if (post_div > pll->max_post_div)
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post_div = pll->max_post_div;
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else if (post_div < pll->min_post_div)
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post_div = pll->min_post_div;
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return post_div;
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}
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#define MAX_TOLERANCE 10
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/**
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* radeon_compute_pll_avivo - compute PLL paramaters
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*
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* @pll: information about the PLL
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* @dot_clock_p: resulting pixel clock
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* fb_div_p: resulting feedback divider
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* frac_fb_div_p: fractional part of the feedback divider
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* ref_div_p: resulting reference divider
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* post_div_p: resulting reference divider
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*
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* Try to calculate the PLL parameters to generate the given frequency:
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* dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
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*/
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void radeon_compute_pll_avivo(struct radeon_pll *pll,
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u32 freq,
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u32 *dot_clock_p,
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@ -867,53 +860,123 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
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u32 *ref_div_p,
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u32 *post_div_p)
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{
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u32 target_clock = freq / 10;
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u32 post_div = avivo_get_post_div(pll, target_clock);
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u32 ref_div = pll->min_ref_div;
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u32 fb_div = 0, frac_fb_div = 0, tmp;
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unsigned fb_div_min, fb_div_max, fb_div;
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unsigned post_div_min, post_div_max, post_div;
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unsigned ref_div_min, ref_div_max, ref_div;
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unsigned post_div_best, diff_best;
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unsigned nom, den, tmp;
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if (pll->flags & RADEON_PLL_USE_REF_DIV)
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ref_div = pll->reference_div;
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/* determine allowed feedback divider range */
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fb_div_min = pll->min_feedback_div;
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fb_div_max = pll->max_feedback_div;
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if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
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avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
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frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
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if (frac_fb_div >= 5) {
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frac_fb_div -= 5;
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frac_fb_div = frac_fb_div / 10;
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frac_fb_div++;
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}
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if (frac_fb_div >= 10) {
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fb_div++;
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frac_fb_div = 0;
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}
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} else {
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while (ref_div <= pll->max_ref_div) {
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avivo_get_fb_div(pll, target_clock, post_div, ref_div,
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&fb_div, &frac_fb_div);
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if (frac_fb_div >= (pll->reference_freq / 2))
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fb_div++;
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frac_fb_div = 0;
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tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
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tmp = (tmp * 10000) / target_clock;
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if (tmp > (10000 + MAX_TOLERANCE))
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ref_div++;
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else if (tmp >= (10000 - MAX_TOLERANCE))
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break;
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else
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ref_div++;
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}
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fb_div_min *= 10;
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fb_div_max *= 10;
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}
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*dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
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(ref_div * post_div * 10);
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*fb_div_p = fb_div;
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*frac_fb_div_p = frac_fb_div;
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/* determine allowed ref divider range */
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if (pll->flags & RADEON_PLL_USE_REF_DIV)
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ref_div_min = pll->reference_div;
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else
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ref_div_min = pll->min_ref_div;
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ref_div_max = pll->max_ref_div;
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/* determine allowed post divider range */
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if (pll->flags & RADEON_PLL_USE_POST_DIV) {
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post_div_min = pll->post_div;
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post_div_max = pll->post_div;
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} else {
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unsigned target_clock = freq / 10;
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unsigned vco_min, vco_max;
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if (pll->flags & RADEON_PLL_IS_LCD) {
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vco_min = pll->lcd_pll_out_min;
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vco_max = pll->lcd_pll_out_max;
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} else {
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vco_min = pll->pll_out_min;
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vco_max = pll->pll_out_max;
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}
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post_div_min = vco_min / target_clock;
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if ((target_clock * post_div_min) < vco_min)
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++post_div_min;
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if (post_div_min < pll->min_post_div)
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post_div_min = pll->min_post_div;
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post_div_max = vco_max / target_clock;
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if ((target_clock * post_div_max) > vco_max)
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--post_div_max;
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if (post_div_max > pll->max_post_div)
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post_div_max = pll->max_post_div;
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}
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/* represent the searched ratio as fractional number */
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nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
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den = pll->reference_freq;
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/* reduce the numbers to a simpler ratio */
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avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
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/* now search for a post divider */
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if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
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post_div_best = post_div_min;
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else
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post_div_best = post_div_max;
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diff_best = ~0;
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for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
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unsigned diff = abs(den - den / post_div * post_div);
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if (diff < diff_best || (diff == diff_best &&
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!(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
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post_div_best = post_div;
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diff_best = diff;
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}
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}
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post_div = post_div_best;
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/* get matching reference and feedback divider */
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ref_div = max(den / post_div, 1u);
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fb_div = nom;
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/* we're almost done, but reference and feedback
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divider might be to large now */
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tmp = ref_div;
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if (fb_div > fb_div_max) {
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ref_div = ref_div * fb_div_max / fb_div;
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fb_div = fb_div_max;
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}
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if (ref_div > ref_div_max) {
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ref_div = ref_div_max;
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fb_div = nom * ref_div_max / tmp;
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}
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/* reduce the numbers to a simpler ratio once more */
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/* this also makes sure that the reference divider is large enough */
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avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
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/* and finally save the result */
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if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
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*fb_div_p = fb_div / 10;
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*frac_fb_div_p = fb_div % 10;
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} else {
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*fb_div_p = fb_div;
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*frac_fb_div_p = 0;
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}
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*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
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(pll->reference_freq * *frac_fb_div_p)) /
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(ref_div * post_div * 10);
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*ref_div_p = ref_div;
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*post_div_p = post_div;
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DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
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*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
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DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
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freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p,
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ref_div, post_div);
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}
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/* pre-avivo */
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