mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 12:43:55 +08:00
drm/ast: resync the dram post code with upstream
This resyncs the dram post code with the upstream X.org driver where ast have improved the code for setting up the dram chips. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
parent
1453bf4c48
commit
318cfa29d0
@ -109,16 +109,25 @@ ast_set_def_ext_reg(struct drm_device *dev)
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static inline u32 mindwm(struct ast_private *ast, u32 r)
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{
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uint32_t data;
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ast_write32(ast, 0xf004, r & 0xffff0000);
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ast_write32(ast, 0xf000, 0x1);
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do {
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data = ast_read32(ast, 0xf004) & 0xffff0000;
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} while (data != (r & 0xffff0000));
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return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
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}
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static inline void moutdwm(struct ast_private *ast, u32 r, u32 v)
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{
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uint32_t data;
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ast_write32(ast, 0xf004, r & 0xffff0000);
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ast_write32(ast, 0xf000, 0x1);
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do {
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data = ast_read32(ast, 0xf004) & 0xffff0000;
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} while (data != (r & 0xffff0000));
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ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
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}
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@ -403,6 +412,7 @@ struct ast2300_dram_param {
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/*
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* DQSI DLL CBR Setting
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*/
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#define CBR_SIZE0 ((1 << 10) - 1)
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#define CBR_SIZE1 ((4 << 10) - 1)
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#define CBR_SIZE2 ((64 << 10) - 1)
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#define CBR_PASSNUM 5
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@ -423,7 +433,6 @@ static const u32 pattern[8] = {
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0x7C61D253
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};
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#if 0 /* unused in DDX, included for completeness */
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static int mmc_test_burst(struct ast_private *ast, u32 datagen)
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{
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u32 data, timeout;
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@ -444,7 +453,6 @@ static int mmc_test_burst(struct ast_private *ast, u32 datagen)
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moutdwm(ast, 0x1e6e0070, 0x00000000);
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return 1;
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}
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#endif
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static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
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{
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@ -466,7 +474,6 @@ static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
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return data;
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}
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#if 0 /* Unused in DDX here for completeness */
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static int mmc_test_single(struct ast_private *ast, u32 datagen)
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{
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u32 data, timeout;
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@ -486,7 +493,6 @@ static int mmc_test_single(struct ast_private *ast, u32 datagen)
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moutdwm(ast, 0x1e6e0070, 0x0);
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return 1;
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}
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#endif
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static int mmc_test_single2(struct ast_private *ast, u32 datagen)
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{
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@ -583,106 +589,35 @@ static u32 cbr_scan2(struct ast_private *ast)
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return data2;
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}
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#if 0 /* unused in DDX - added for completeness */
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static void finetuneDQI(struct ast_private *ast, struct ast2300_dram_param *param)
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static u32 cbr_test3(struct ast_private *ast)
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{
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u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt;
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if (!mmc_test_burst(ast, 0))
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return 0;
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if (!mmc_test_single(ast, 0))
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return 0;
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return 1;
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}
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gold_sadj[0] = (mindwm(ast, 0x1E6E0024) >> 16) & 0xffff;
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gold_sadj[1] = gold_sadj[0] >> 8;
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gold_sadj[0] = gold_sadj[0] & 0xff;
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gold_sadj[0] = (gold_sadj[0] + gold_sadj[1]) >> 1;
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gold_sadj[1] = gold_sadj[0];
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for (cnt = 0; cnt < 16; cnt++) {
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dllmin[cnt] = 0xff;
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dllmax[cnt] = 0x0;
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}
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passcnt = 0;
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for (dlli = 0; dlli < 76; dlli++) {
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moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
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/* Wait DQSI latch phase calibration */
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moutdwm(ast, 0x1E6E0074, 0x00000010);
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moutdwm(ast, 0x1E6E0070, 0x00000003);
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do {
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data = mindwm(ast, 0x1E6E0070);
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} while (!(data & 0x00001000));
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moutdwm(ast, 0x1E6E0070, 0x00000000);
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moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
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data = cbr_scan2(ast);
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if (data != 0) {
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mask = 0x00010001;
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for (cnt = 0; cnt < 16; cnt++) {
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if (data & mask) {
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if (dllmin[cnt] > dlli) {
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dllmin[cnt] = dlli;
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}
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if (dllmax[cnt] < dlli) {
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dllmax[cnt] = dlli;
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}
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}
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mask <<= 1;
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}
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passcnt++;
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} else if (passcnt >= CBR_THRESHOLD) {
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break;
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}
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}
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data = 0;
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for (cnt = 0; cnt < 8; cnt++) {
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data >>= 3;
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if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) {
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dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
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if (gold_sadj[0] >= dlli) {
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dlli = (gold_sadj[0] - dlli) >> 1;
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if (dlli > 3) {
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dlli = 3;
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}
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} else {
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dlli = (dlli - gold_sadj[0]) >> 1;
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if (dlli > 4) {
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dlli = 4;
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}
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dlli = (8 - dlli) & 0x7;
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}
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data |= dlli << 21;
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}
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}
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moutdwm(ast, 0x1E6E0080, data);
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data = 0;
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for (cnt = 8; cnt < 16; cnt++) {
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data >>= 3;
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if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) {
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dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
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if (gold_sadj[1] >= dlli) {
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dlli = (gold_sadj[1] - dlli) >> 1;
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if (dlli > 3) {
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dlli = 3;
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} else {
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dlli = (dlli - 1) & 0x7;
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}
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} else {
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dlli = (dlli - gold_sadj[1]) >> 1;
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dlli += 1;
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if (dlli > 4) {
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dlli = 4;
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}
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dlli = (8 - dlli) & 0x7;
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}
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data |= dlli << 21;
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}
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}
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moutdwm(ast, 0x1E6E0084, data);
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} /* finetuneDQI */
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#endif
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static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
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static u32 cbr_scan3(struct ast_private *ast)
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{
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u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt;
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u32 patcnt, loop;
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for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
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moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
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for (loop = 0; loop < 2; loop++) {
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if (cbr_test3(ast))
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break;
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}
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if (loop == 2)
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return 0;
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}
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return 1;
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}
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static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
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{
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u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
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bool status = false;
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FINETUNE_START:
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for (cnt = 0; cnt < 16; cnt++) {
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dllmin[cnt] = 0xff;
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@ -691,14 +626,6 @@ FINETUNE_START:
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passcnt = 0;
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for (dlli = 0; dlli < 76; dlli++) {
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moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
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/* Wait DQSI latch phase calibration */
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moutdwm(ast, 0x1E6E0074, 0x00000010);
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moutdwm(ast, 0x1E6E0070, 0x00000003);
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do {
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data = mindwm(ast, 0x1E6E0070);
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} while (!(data & 0x00001000));
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moutdwm(ast, 0x1E6E0070, 0x00000000);
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moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
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data = cbr_scan2(ast);
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if (data != 0) {
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@ -727,9 +654,13 @@ FINETUNE_START:
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passcnt++;
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}
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}
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if (retry++ > 10)
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goto FINETUNE_DONE;
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if (passcnt != 16) {
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goto FINETUNE_START;
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}
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status = true;
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FINETUNE_DONE:
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gold_sadj[0] = gold_sadj[0] >> 4;
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gold_sadj[1] = gold_sadj[0];
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@ -779,145 +710,107 @@ FINETUNE_START:
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}
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}
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moutdwm(ast, 0x1E6E0084, data);
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return status;
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} /* finetuneDQI_L */
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static void finetuneDQI_L2(struct ast_private *ast, struct ast2300_dram_param *param)
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static void finetuneDQSI(struct ast_private *ast)
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{
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u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, data2;
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u32 dlli, dqsip, dqidly;
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u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
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u32 g_dqidly, g_dqsip, g_margin, g_side;
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u16 pass[32][2][2];
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char tag[2][76];
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/* Disable DQI CBR */
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reg_mcr0c = mindwm(ast, 0x1E6E000C);
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reg_mcr18 = mindwm(ast, 0x1E6E0018);
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reg_mcr18 &= 0x0000ffff;
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moutdwm(ast, 0x1E6E0018, reg_mcr18);
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for (cnt = 0; cnt < 16; cnt++) {
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dllmin[cnt] = 0xff;
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dllmax[cnt] = 0x0;
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}
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passcnt = 0;
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for (dlli = 0; dlli < 76; dlli++) {
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moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
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/* Wait DQSI latch phase calibration */
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moutdwm(ast, 0x1E6E0074, 0x00000010);
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moutdwm(ast, 0x1E6E0070, 0x00000003);
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do {
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data = mindwm(ast, 0x1E6E0070);
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} while (!(data & 0x00001000));
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moutdwm(ast, 0x1E6E0070, 0x00000000);
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moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
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data = cbr_scan2(ast);
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if (data != 0) {
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mask = 0x00010001;
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for (cnt = 0; cnt < 16; cnt++) {
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if (data & mask) {
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if (dllmin[cnt] > dlli) {
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dllmin[cnt] = dlli;
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}
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if (dllmax[cnt] < dlli) {
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dllmax[cnt] = dlli;
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}
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}
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mask <<= 1;
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}
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passcnt++;
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} else if (passcnt >= CBR_THRESHOLD2) {
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break;
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}
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tag[0][dlli] = 0x0;
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tag[1][dlli] = 0x0;
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}
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gold_sadj[0] = 0x0;
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gold_sadj[1] = 0xFF;
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for (cnt = 0; cnt < 8; cnt++) {
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if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
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if (gold_sadj[0] < dllmin[cnt]) {
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gold_sadj[0] = dllmin[cnt];
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}
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if (gold_sadj[1] > dllmax[cnt]) {
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gold_sadj[1] = dllmax[cnt];
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}
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}
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for (dqidly = 0; dqidly < 32; dqidly++) {
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pass[dqidly][0][0] = 0xff;
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pass[dqidly][0][1] = 0x0;
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pass[dqidly][1][0] = 0xff;
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pass[dqidly][1][1] = 0x0;
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}
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gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1;
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gold_sadj[1] = mindwm(ast, 0x1E6E0080);
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data = 0;
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for (cnt = 0; cnt < 8; cnt++) {
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data >>= 3;
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data2 = gold_sadj[1] & 0x7;
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gold_sadj[1] >>= 3;
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if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
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dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
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if (gold_sadj[0] >= dlli) {
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dlli = (gold_sadj[0] - dlli) >> 1;
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if (dlli > 0) {
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dlli = 1;
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}
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if (data2 != 3) {
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data2 = (data2 + dlli) & 0x7;
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}
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} else {
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dlli = (dlli - gold_sadj[0]) >> 1;
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if (dlli > 0) {
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dlli = 1;
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}
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if (data2 != 4) {
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data2 = (data2 - dlli) & 0x7;
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for (dqidly = 0; dqidly < 32; dqidly++) {
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passcnt[0] = passcnt[1] = 0;
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for (dqsip = 0; dqsip < 2; dqsip++) {
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moutdwm(ast, 0x1E6E000C, 0);
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moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
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moutdwm(ast, 0x1E6E000C, reg_mcr0c);
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for (dlli = 0; dlli < 76; dlli++) {
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moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
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moutdwm(ast, 0x1E6E0070, 0);
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moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
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if (cbr_scan3(ast)) {
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if (dlli == 0)
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break;
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passcnt[dqsip]++;
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tag[dqsip][dlli] = 'P';
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if (dlli < pass[dqidly][dqsip][0])
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pass[dqidly][dqsip][0] = (u16) dlli;
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if (dlli > pass[dqidly][dqsip][1])
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pass[dqidly][dqsip][1] = (u16) dlli;
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} else if (passcnt[dqsip] >= 5)
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break;
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else {
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pass[dqidly][dqsip][0] = 0xff;
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pass[dqidly][dqsip][1] = 0x0;
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}
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}
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}
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data |= data2 << 21;
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if (passcnt[0] == 0 && passcnt[1] == 0)
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dqidly++;
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}
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moutdwm(ast, 0x1E6E0080, data);
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/* Search margin */
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g_dqidly = g_dqsip = g_margin = g_side = 0;
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gold_sadj[0] = 0x0;
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gold_sadj[1] = 0xFF;
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for (cnt = 8; cnt < 16; cnt++) {
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if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
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if (gold_sadj[0] < dllmin[cnt]) {
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gold_sadj[0] = dllmin[cnt];
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}
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if (gold_sadj[1] > dllmax[cnt]) {
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gold_sadj[1] = dllmax[cnt];
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for (dqidly = 0; dqidly < 32; dqidly++) {
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for (dqsip = 0; dqsip < 2; dqsip++) {
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if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
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continue;
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diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
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if ((diff+2) < g_margin)
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continue;
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passcnt[0] = passcnt[1] = 0;
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for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
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for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
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if (passcnt[0] > passcnt[1])
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passcnt[0] = passcnt[1];
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passcnt[1] = 0;
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if (passcnt[0] > g_side)
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passcnt[1] = passcnt[0] - g_side;
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if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
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g_margin = diff;
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g_dqidly = dqidly;
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g_dqsip = dqsip;
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g_side = passcnt[0];
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} else if (passcnt[1] > 1 && g_side < 8) {
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if (diff > g_margin)
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g_margin = diff;
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g_dqidly = dqidly;
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g_dqsip = dqsip;
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g_side = passcnt[0];
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}
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}
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}
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gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1;
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gold_sadj[1] = mindwm(ast, 0x1E6E0084);
|
||||
reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
|
||||
moutdwm(ast, 0x1E6E0018, reg_mcr18);
|
||||
|
||||
data = 0;
|
||||
for (cnt = 8; cnt < 16; cnt++) {
|
||||
data >>= 3;
|
||||
data2 = gold_sadj[1] & 0x7;
|
||||
gold_sadj[1] >>= 3;
|
||||
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
|
||||
dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
|
||||
if (gold_sadj[0] >= dlli) {
|
||||
dlli = (gold_sadj[0] - dlli) >> 1;
|
||||
if (dlli > 0) {
|
||||
dlli = 1;
|
||||
}
|
||||
if (data2 != 3) {
|
||||
data2 = (data2 + dlli) & 0x7;
|
||||
}
|
||||
} else {
|
||||
dlli = (dlli - gold_sadj[0]) >> 1;
|
||||
if (dlli > 0) {
|
||||
dlli = 1;
|
||||
}
|
||||
if (data2 != 4) {
|
||||
data2 = (data2 - dlli) & 0x7;
|
||||
}
|
||||
}
|
||||
}
|
||||
data |= data2 << 21;
|
||||
}
|
||||
moutdwm(ast, 0x1E6E0084, data);
|
||||
|
||||
} /* finetuneDQI_L2 */
|
||||
|
||||
static void cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
}
|
||||
static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
{
|
||||
u32 dllmin[2], dllmax[2], dlli, data, data2, passcnt;
|
||||
u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
|
||||
bool status = false;
|
||||
|
||||
|
||||
finetuneDQI_L(ast, param);
|
||||
finetuneDQI_L2(ast, param);
|
||||
finetuneDQSI(ast);
|
||||
if (finetuneDQI_L(ast, param) == false)
|
||||
return status;
|
||||
|
||||
CBR_START2:
|
||||
dllmin[0] = dllmin[1] = 0xff;
|
||||
@ -925,14 +818,6 @@ CBR_START2:
|
||||
passcnt = 0;
|
||||
for (dlli = 0; dlli < 76; dlli++) {
|
||||
moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
|
||||
/* Wait DQSI latch phase calibration */
|
||||
moutdwm(ast, 0x1E6E0074, 0x00000010);
|
||||
moutdwm(ast, 0x1E6E0070, 0x00000003);
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E0070);
|
||||
} while (!(data & 0x00001000));
|
||||
moutdwm(ast, 0x1E6E0070, 0x00000000);
|
||||
|
||||
moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
|
||||
data = cbr_scan(ast);
|
||||
if (data != 0) {
|
||||
@ -957,34 +842,21 @@ CBR_START2:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (retry++ > 10)
|
||||
goto CBR_DONE2;
|
||||
if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
|
||||
goto CBR_START2;
|
||||
}
|
||||
if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
|
||||
goto CBR_START2;
|
||||
}
|
||||
status = true;
|
||||
CBR_DONE2:
|
||||
dlli = (dllmin[1] + dllmax[1]) >> 1;
|
||||
dlli <<= 8;
|
||||
dlli += (dllmin[0] + dllmax[0]) >> 1;
|
||||
moutdwm(ast, 0x1E6E0068, (mindwm(ast, 0x1E6E0068) & 0xFFFF) | (dlli << 16));
|
||||
|
||||
data = (mindwm(ast, 0x1E6E0080) >> 24) & 0x1F;
|
||||
data2 = (mindwm(ast, 0x1E6E0018) & 0xff80ffff) | (data << 16);
|
||||
moutdwm(ast, 0x1E6E0018, data2);
|
||||
moutdwm(ast, 0x1E6E0024, 0x8001 | (data << 1) | (param->dll2_finetune_step << 8));
|
||||
|
||||
/* Wait DQSI latch phase calibration */
|
||||
moutdwm(ast, 0x1E6E0074, 0x00000010);
|
||||
moutdwm(ast, 0x1E6E0070, 0x00000003);
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E0070);
|
||||
} while (!(data & 0x00001000));
|
||||
moutdwm(ast, 0x1E6E0070, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0070, 0x00000003);
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E0070);
|
||||
} while (!(data & 0x00001000));
|
||||
moutdwm(ast, 0x1E6E0070, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0068, mindwm(ast, 0x1E720058) | (dlli << 16));
|
||||
return status;
|
||||
} /* CBRDLL2 */
|
||||
|
||||
static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
@ -1015,11 +887,24 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
|
||||
param->reg_DQSIC = 0x000000BA;
|
||||
param->reg_MRS = 0x04001400 | trap_MRS;
|
||||
param->reg_EMRS = 0x00000000;
|
||||
param->reg_IOZ = 0x00000034;
|
||||
param->reg_IOZ = 0x00000023;
|
||||
param->reg_DQIDLY = 0x00000074;
|
||||
param->reg_FREQ = 0x00004DC0;
|
||||
param->madj_max = 96;
|
||||
param->dll2_finetune_step = 3;
|
||||
switch (param->dram_chipid) {
|
||||
default:
|
||||
case AST_DRAM_512Mx16:
|
||||
case AST_DRAM_1Gx16:
|
||||
param->reg_AC2 = 0xAA007613 | trap_AC2;
|
||||
break;
|
||||
case AST_DRAM_2Gx16:
|
||||
param->reg_AC2 = 0xAA00761C | trap_AC2;
|
||||
break;
|
||||
case AST_DRAM_4Gx16:
|
||||
param->reg_AC2 = 0xAA007636 | trap_AC2;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
case 396:
|
||||
@ -1033,7 +918,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
|
||||
param->reg_IOZ = 0x00000034;
|
||||
param->reg_DRV = 0x000000FA;
|
||||
param->reg_DQIDLY = 0x00000089;
|
||||
param->reg_FREQ = 0x000050C0;
|
||||
param->reg_FREQ = 0x00005040;
|
||||
param->madj_max = 96;
|
||||
param->dll2_finetune_step = 4;
|
||||
|
||||
@ -1060,7 +945,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
|
||||
param->reg_DQSIC = 0x000000E2;
|
||||
param->reg_MRS = 0x04001600 | trap_MRS;
|
||||
param->reg_EMRS = 0x00000000;
|
||||
param->reg_IOZ = 0x00000034;
|
||||
param->reg_IOZ = 0x00000023;
|
||||
param->reg_DRV = 0x000000FA;
|
||||
param->reg_DQIDLY = 0x00000089;
|
||||
param->reg_FREQ = 0x000050C0;
|
||||
@ -1218,8 +1103,9 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
|
||||
|
||||
static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
{
|
||||
u32 data, data2;
|
||||
u32 data, data2, retry = 0;
|
||||
|
||||
ddr3_init_start:
|
||||
moutdwm(ast, 0x1E6E0000, 0xFC600309);
|
||||
moutdwm(ast, 0x1E6E0018, 0x00000100);
|
||||
moutdwm(ast, 0x1E6E0024, 0x00000000);
|
||||
@ -1239,8 +1125,8 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
moutdwm(ast, 0x1E6E0080, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0084, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
|
||||
moutdwm(ast, 0x1E6E0018, 0x4040A170);
|
||||
moutdwm(ast, 0x1E6E0018, 0x20402370);
|
||||
moutdwm(ast, 0x1E6E0018, 0x4000A170);
|
||||
moutdwm(ast, 0x1E6E0018, 0x00002370);
|
||||
moutdwm(ast, 0x1E6E0038, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0040, 0xFF444444);
|
||||
moutdwm(ast, 0x1E6E0044, 0x22222222);
|
||||
@ -1259,11 +1145,6 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E001C);
|
||||
} while (!(data & 0x08000000));
|
||||
moutdwm(ast, 0x1E6E0034, 0x00000001);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00005C04);
|
||||
udelay(10);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0034, 0x00000000);
|
||||
data = mindwm(ast, 0x1E6E001C);
|
||||
data = (data >> 8) & 0xff;
|
||||
while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
|
||||
@ -1292,14 +1173,10 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
data = mindwm(ast, 0x1E6E001C);
|
||||
} while (!(data & 0x08000000));
|
||||
|
||||
moutdwm(ast, 0x1E6E0034, 0x00000001);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00005C04);
|
||||
udelay(10);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0034, 0x00000000);
|
||||
data = mindwm(ast, 0x1E6E001C);
|
||||
data = (data >> 8) & 0xff;
|
||||
}
|
||||
moutdwm(ast, 0x1E720058, mindwm(ast, 0x1E6E0068) & 0xffff);
|
||||
data = mindwm(ast, 0x1E6E0018) | 0xC00;
|
||||
moutdwm(ast, 0x1E6E0018, data);
|
||||
|
||||
@ -1317,7 +1194,7 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
moutdwm(ast, 0x1E6E000C, 0x00005C08);
|
||||
moutdwm(ast, 0x1E6E0028, 0x00000001);
|
||||
|
||||
moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00005C01);
|
||||
data = 0;
|
||||
if (param->wodt) {
|
||||
data = 0x300;
|
||||
@ -1327,16 +1204,9 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
}
|
||||
moutdwm(ast, 0x1E6E0034, data | 0x3);
|
||||
|
||||
/* Wait DQI delay lock */
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E0080);
|
||||
} while (!(data & 0x40000000));
|
||||
/* Wait DQSI delay lock */
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E0020);
|
||||
} while (!(data & 0x00000800));
|
||||
/* Calibrate the DQSI delay */
|
||||
cbr_dll2(ast, param);
|
||||
if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
|
||||
goto ddr3_init_start;
|
||||
|
||||
moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
|
||||
/* ECC Memory Initialization */
|
||||
@ -1403,6 +1273,21 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
|
||||
param->reg_FREQ = 0x00004DC0;
|
||||
param->madj_max = 96;
|
||||
param->dll2_finetune_step = 3;
|
||||
switch (param->dram_chipid) {
|
||||
default:
|
||||
case AST_DRAM_512Mx16:
|
||||
param->reg_AC2 = 0xAA009012 | trap_AC2;
|
||||
break;
|
||||
case AST_DRAM_1Gx16:
|
||||
param->reg_AC2 = 0xAA009016 | trap_AC2;
|
||||
break;
|
||||
case AST_DRAM_2Gx16:
|
||||
param->reg_AC2 = 0xAA009023 | trap_AC2;
|
||||
break;
|
||||
case AST_DRAM_4Gx16:
|
||||
param->reg_AC2 = 0xAA00903B | trap_AC2;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
case 396:
|
||||
@ -1417,7 +1302,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
|
||||
param->reg_DRV = 0x000000FA;
|
||||
param->reg_IOZ = 0x00000034;
|
||||
param->reg_DQIDLY = 0x00000089;
|
||||
param->reg_FREQ = 0x000050C0;
|
||||
param->reg_FREQ = 0x00005040;
|
||||
param->madj_max = 96;
|
||||
param->dll2_finetune_step = 4;
|
||||
|
||||
@ -1588,8 +1473,9 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
|
||||
|
||||
static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
{
|
||||
u32 data, data2;
|
||||
u32 data, data2, retry = 0;
|
||||
|
||||
ddr2_init_start:
|
||||
moutdwm(ast, 0x1E6E0000, 0xFC600309);
|
||||
moutdwm(ast, 0x1E6E0018, 0x00000100);
|
||||
moutdwm(ast, 0x1E6E0024, 0x00000000);
|
||||
@ -1607,8 +1493,8 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
moutdwm(ast, 0x1E6E0080, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0084, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
|
||||
moutdwm(ast, 0x1E6E0018, 0x4040A130);
|
||||
moutdwm(ast, 0x1E6E0018, 0x20402330);
|
||||
moutdwm(ast, 0x1E6E0018, 0x4000A130);
|
||||
moutdwm(ast, 0x1E6E0018, 0x00002330);
|
||||
moutdwm(ast, 0x1E6E0038, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0040, 0xFF808000);
|
||||
moutdwm(ast, 0x1E6E0044, 0x88848466);
|
||||
@ -1628,11 +1514,6 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E001C);
|
||||
} while (!(data & 0x08000000));
|
||||
moutdwm(ast, 0x1E6E0034, 0x00000001);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00005C04);
|
||||
udelay(10);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0034, 0x00000000);
|
||||
data = mindwm(ast, 0x1E6E001C);
|
||||
data = (data >> 8) & 0xff;
|
||||
while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
|
||||
@ -1661,14 +1542,10 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
data = mindwm(ast, 0x1E6E001C);
|
||||
} while (!(data & 0x08000000));
|
||||
|
||||
moutdwm(ast, 0x1E6E0034, 0x00000001);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00005C04);
|
||||
udelay(10);
|
||||
moutdwm(ast, 0x1E6E000C, 0x00000000);
|
||||
moutdwm(ast, 0x1E6E0034, 0x00000000);
|
||||
data = mindwm(ast, 0x1E6E001C);
|
||||
data = (data >> 8) & 0xff;
|
||||
}
|
||||
moutdwm(ast, 0x1E720058, mindwm(ast, 0x1E6E0008) & 0xffff);
|
||||
data = mindwm(ast, 0x1E6E0018) | 0xC00;
|
||||
moutdwm(ast, 0x1E6E0018, data);
|
||||
|
||||
@ -1702,16 +1579,9 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
|
||||
moutdwm(ast, 0x1E6E0034, data | 0x3);
|
||||
moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
|
||||
|
||||
/* Wait DQI delay lock */
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E0080);
|
||||
} while (!(data & 0x40000000));
|
||||
/* Wait DQSI delay lock */
|
||||
do {
|
||||
data = mindwm(ast, 0x1E6E0020);
|
||||
} while (!(data & 0x00000800));
|
||||
/* Calibrate the DQSI delay */
|
||||
cbr_dll2(ast, param);
|
||||
if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
|
||||
goto ddr2_init_start;
|
||||
|
||||
/* ECC Memory Initialization */
|
||||
#ifdef ECC
|
||||
|
||||
Loading…
Reference in New Issue
Block a user