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ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants
And move them out of cmpxchg.h to canonical atomic.h Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
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@ -22,6 +22,33 @@
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#include <asm/atomic-spinlock.h>
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#endif
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#define arch_atomic_cmpxchg(v, o, n) \
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({ \
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arch_cmpxchg(&((v)->counter), (o), (n)); \
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})
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#ifdef arch_cmpxchg_relaxed
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#define arch_atomic_cmpxchg_relaxed(v, o, n) \
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({ \
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arch_cmpxchg_relaxed(&((v)->counter), (o), (n)); \
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})
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#endif
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#define arch_atomic_xchg(v, n) \
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({ \
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arch_xchg(&((v)->counter), (n)); \
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})
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#ifdef arch_xchg_relaxed
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#define arch_atomic_xchg_relaxed(v, n) \
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({ \
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arch_xchg_relaxed(&((v)->counter), (n)); \
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})
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#endif
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/*
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* 64-bit atomics
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*/
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#ifdef CONFIG_GENERIC_ATOMIC64
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#include <asm-generic/atomic64.h>
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#else
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@ -80,14 +80,6 @@
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#endif
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/*
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* atomic_cmpxchg is same as cmpxchg
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* LLSC: only different in data-type, semantics are exactly same
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* !LLSC: cmpxchg() has to use an external lock atomic_ops_lock to guarantee
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* semantics, and this lock also happens to be used by atomic_*()
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*/
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#define arch_atomic_cmpxchg(v, o, n) ((int)arch_cmpxchg(&((v)->counter), (o), (n)))
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/*
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* xchg
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*/
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@ -148,19 +140,4 @@
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#endif
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/*
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* "atomic" variant of xchg()
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* REQ: It needs to follow the same serialization rules as other atomic_xxx()
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* Since xchg() doesn't always do that, it would seem that following definition
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* is incorrect. But here's the rationale:
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* SMP : Even xchg() takes the atomic_ops_lock, so OK.
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* LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC
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* is natively "SMP safe", no serialization required).
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* UP : other atomics disable IRQ, so no way a difft ctxt atomic_xchg()
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* could clobber them. atomic_xchg() itself would be 1 insn, so it
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* can't be clobbered by others. Thus no serialization required when
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* atomic_xchg is involved.
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*/
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#define arch_atomic_xchg(v, new) (arch_xchg(&((v)->counter), new))
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#endif
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