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staging: fbtft: add fb_ili9325 driver
This commit adds the fb_ili9325 driver from the fbtft project at https://github.com/notro/fbtft. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Noralf Tronnes <notro@tronnes.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Thomas Petazzoni
Greg Kroah-Hartman
parent
69e6089d20
commit
2fc51f76cf
@ -43,3 +43,9 @@ config FB_TFT_ILI9320
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depends on FB_TFT
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help
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Generic Framebuffer support for ILI9320
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config FB_TFT_ILI9325
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tristate "FB driver for the ILI9325 LCD Controller"
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depends on FB_TFT
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help
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Generic Framebuffer support for ILI9325
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@ -9,3 +9,4 @@ obj-$(CONFIG_FB_TFT_HX8340BN) += fb_hx8340bn.o
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obj-$(CONFIG_FB_TFT_HX8347D) += fb_hx8347d.o
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obj-$(CONFIG_FB_TFT_HX8353D) += fb_hx8353d.o
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obj-$(CONFIG_FB_TFT_ILI9320) += fb_ili9320.o
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obj-$(CONFIG_FB_TFT_ILI9325) += fb_ili9325.o
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291
drivers/staging/fbtft/fb_ili9325.c
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291
drivers/staging/fbtft/fb_ili9325.c
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@ -0,0 +1,291 @@
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/*
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* FB driver for the ILI9325 LCD Controller
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*
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* Copyright (C) 2013 Noralf Tronnes
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*
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* Based on ili9325.c by Jeroen Domburg
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include "fbtft.h"
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#define DRVNAME "fb_ili9325"
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#define WIDTH 240
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#define HEIGHT 320
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#define BPP 16
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#define FPS 20
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#define DEFAULT_GAMMA "0F 00 7 2 0 0 6 5 4 1\n" \
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"04 16 2 7 6 3 2 1 7 7"
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static unsigned bt = 6; /* VGL=Vci*4 , VGH=Vci*4 */
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module_param(bt, uint, 0);
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MODULE_PARM_DESC(bt, "Sets the factor used in the step-up circuits");
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static unsigned vc = 0b011; /* Vci1=Vci*0.80 */
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module_param(vc, uint, 0);
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MODULE_PARM_DESC(vc,
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"Sets the ratio factor of Vci to generate the reference voltages Vci1");
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static unsigned vrh = 0b1101; /* VREG1OUT=Vci*1.85 */
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module_param(vrh, uint, 0);
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MODULE_PARM_DESC(vrh,
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"Set the amplifying rate (1.6 ~ 1.9) of Vci applied to output the VREG1OUT");
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static unsigned vdv = 0b10010; /* VCOMH amplitude=VREG1OUT*0.98 */
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module_param(vdv, uint, 0);
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MODULE_PARM_DESC(vdv,
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"Select the factor of VREG1OUT to set the amplitude of Vcom");
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static unsigned vcm = 0b001010; /* VCOMH=VREG1OUT*0.735 */
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module_param(vcm, uint, 0);
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MODULE_PARM_DESC(vcm, "Set the internal VcomH voltage");
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/*
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Verify that this configuration is within the Voltage limits
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Display module configuration: Vcc = IOVcc = Vci = 3.3V
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Voltages
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----------
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Vci = 3.3
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Vci1 = Vci * 0.80 = 2.64
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DDVDH = Vci1 * 2 = 5.28
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VCL = -Vci1 = -2.64
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VREG1OUT = Vci * 1.85 = 4.88
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VCOMH = VREG1OUT * 0.735 = 3.59
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VCOM amplitude = VREG1OUT * 0.98 = 4.79
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VGH = Vci * 4 = 13.2
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VGL = -Vci * 4 = -13.2
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Limits
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--------
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Power supplies
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1.65 < IOVcc < 3.30 => 1.65 < 3.3 < 3.30
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2.40 < Vcc < 3.30 => 2.40 < 3.3 < 3.30
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2.50 < Vci < 3.30 => 2.50 < 3.3 < 3.30
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Source/VCOM power supply voltage
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4.50 < DDVDH < 6.0 => 4.50 < 5.28 < 6.0
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-3.0 < VCL < -2.0 => -3.0 < -2.64 < -2.0
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VCI - VCL < 6.0 => 5.94 < 6.0
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Gate driver output voltage
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10 < VGH < 20 => 10 < 13.2 < 20
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-15 < VGL < -5 => -15 < -13.2 < -5
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VGH - VGL < 32 => 26.4 < 32
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VCOM driver output voltage
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VCOMH - VCOML < 6.0 => 4.79 < 6.0
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*/
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static int init_display(struct fbtft_par *par)
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{
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fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
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par->fbtftops.reset(par);
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if (par->gpio.cs != -1)
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gpio_set_value(par->gpio.cs, 0); /* Activate chip */
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bt &= 0b111;
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vc &= 0b111;
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vrh &= 0b1111;
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vdv &= 0b11111;
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vcm &= 0b111111;
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/* Initialization sequence from ILI9325 Application Notes */
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/* ----------- Start Initial Sequence ----------- */
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write_reg(par, 0x00E3, 0x3008); /* Set internal timing */
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write_reg(par, 0x00E7, 0x0012); /* Set internal timing */
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write_reg(par, 0x00EF, 0x1231); /* Set internal timing */
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write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */
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write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */
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write_reg(par, 0x0004, 0x0000); /* Resize register */
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write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */
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write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */
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write_reg(par, 0x000A, 0x0000); /* FMARK function */
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write_reg(par, 0x000C, 0x0000); /* RGB interface setting */
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write_reg(par, 0x000D, 0x0000); /* Frame marker Position */
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write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */
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/* ----------- Power On sequence ----------- */
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write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
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write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
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write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */
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write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */
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mdelay(200); /* Dis-charge capacitor power voltage */
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write_reg(par, 0x0010, /* SAP, BT[3:0], AP, DSTB, SLP, STB */
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(1 << 12) | (bt << 8) | (1 << 7) | (0b001 << 4));
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write_reg(par, 0x0011, 0x220 | vc); /* DC1[2:0], DC0[2:0], VC[2:0] */
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mdelay(50); /* Delay 50ms */
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write_reg(par, 0x0012, vrh); /* Internal reference voltage= Vci; */
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mdelay(50); /* Delay 50ms */
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write_reg(par, 0x0013, vdv << 8); /* Set VDV[4:0] for VCOM amplitude */
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write_reg(par, 0x0029, vcm); /* Set VCM[5:0] for VCOMH */
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write_reg(par, 0x002B, 0x000C); /* Set Frame Rate */
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mdelay(50); /* Delay 50ms */
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write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */
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write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */
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/*------------------ Set GRAM area --------------- */
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write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */
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write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */
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write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */
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write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */
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write_reg(par, 0x0060, 0xA700); /* Gate Scan Line */
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write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */
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write_reg(par, 0x006A, 0x0000); /* set scrolling line */
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/*-------------- Partial Display Control --------- */
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write_reg(par, 0x0080, 0x0000);
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write_reg(par, 0x0081, 0x0000);
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write_reg(par, 0x0082, 0x0000);
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write_reg(par, 0x0083, 0x0000);
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write_reg(par, 0x0084, 0x0000);
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write_reg(par, 0x0085, 0x0000);
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/*-------------- Panel Control ------------------- */
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write_reg(par, 0x0090, 0x0010);
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write_reg(par, 0x0092, 0x0600);
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write_reg(par, 0x0007, 0x0133); /* 262K color and display ON */
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return 0;
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}
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static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
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{
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fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
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"%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
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switch (par->info->var.rotate) {
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/* R20h = Horizontal GRAM Start Address */
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/* R21h = Vertical GRAM Start Address */
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case 0:
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write_reg(par, 0x0020, xs);
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write_reg(par, 0x0021, ys);
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break;
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case 180:
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write_reg(par, 0x0020, WIDTH - 1 - xs);
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write_reg(par, 0x0021, HEIGHT - 1 - ys);
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break;
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case 270:
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write_reg(par, 0x0020, WIDTH - 1 - ys);
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write_reg(par, 0x0021, xs);
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break;
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case 90:
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write_reg(par, 0x0020, ys);
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write_reg(par, 0x0021, HEIGHT - 1 - xs);
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break;
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}
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write_reg(par, 0x0022); /* Write Data to GRAM */
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}
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static int set_var(struct fbtft_par *par)
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{
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fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
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switch (par->info->var.rotate) {
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/* AM: GRAM update direction */
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case 0:
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write_reg(par, 0x03, 0x0030 | (par->bgr << 12));
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break;
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case 180:
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write_reg(par, 0x03, 0x0000 | (par->bgr << 12));
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break;
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case 270:
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write_reg(par, 0x03, 0x0028 | (par->bgr << 12));
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break;
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case 90:
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write_reg(par, 0x03, 0x0018 | (par->bgr << 12));
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break;
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}
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return 0;
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}
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/*
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Gamma string format:
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VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
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VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
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*/
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#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
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static int set_gamma(struct fbtft_par *par, unsigned long *curves)
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{
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unsigned long mask[] = {
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0b11111, 0b11111, 0b111, 0b111, 0b111,
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0b111, 0b111, 0b111, 0b111, 0b111,
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0b11111, 0b11111, 0b111, 0b111, 0b111,
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0b111, 0b111, 0b111, 0b111, 0b111 };
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int i, j;
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fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
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/* apply mask */
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for (i = 0; i < 2; i++)
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for (j = 0; j < 10; j++)
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CURVE(i, j) &= mask[i*par->gamma.num_values + j];
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write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
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write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
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write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
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write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
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write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
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write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
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write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
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write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
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write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
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write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));
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return 0;
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}
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#undef CURVE
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static struct fbtft_display display = {
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.regwidth = 16,
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.width = WIDTH,
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.height = HEIGHT,
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.bpp = BPP,
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.fps = FPS,
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.gamma_num = 2,
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.gamma_len = 10,
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.gamma = DEFAULT_GAMMA,
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.fbtftops = {
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.init_display = init_display,
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.set_addr_win = set_addr_win,
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.set_var = set_var,
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.set_gamma = set_gamma,
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},
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};
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FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9325", &display);
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MODULE_ALIAS("spi:" DRVNAME);
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MODULE_ALIAS("platform:" DRVNAME);
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MODULE_ALIAS("spi:ili9325");
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MODULE_ALIAS("platform:ili9325");
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MODULE_DESCRIPTION("FB driver for the ILI9325 LCD Controller");
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MODULE_AUTHOR("Noralf Tronnes");
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MODULE_LICENSE("GPL");
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