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drm/i2c: tda998x: simplify the i2c read/write functions
This patch simplifies the i2c read/write functions and permits them to be easily called in more contexts. Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Jean-Francois Moine
Russell King
parent
f0b33b282c
commit
2f7f730a4f
@ -31,6 +31,7 @@
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struct tda998x_priv {
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struct i2c_client *cec;
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struct i2c_client *hdmi;
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uint16_t rev;
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uint8_t current_page;
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int dpms;
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@ -329,9 +330,9 @@ struct tda998x_priv {
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#define TDA19988 0x0301
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static void
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cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val)
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cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val)
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{
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struct i2c_client *client = to_tda998x_priv(encoder)->cec;
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struct i2c_client *client = priv->cec;
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uint8_t buf[] = {addr, val};
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int ret;
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@ -341,9 +342,9 @@ cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val)
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}
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static uint8_t
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cec_read(struct drm_encoder *encoder, uint8_t addr)
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cec_read(struct tda998x_priv *priv, uint8_t addr)
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{
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struct i2c_client *client = to_tda998x_priv(encoder)->cec;
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struct i2c_client *client = priv->cec;
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uint8_t val;
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int ret;
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@ -363,12 +364,10 @@ fail:
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}
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static void
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set_page(struct drm_encoder *encoder, uint16_t reg)
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set_page(struct tda998x_priv *priv, uint16_t reg)
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{
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struct tda998x_priv *priv = to_tda998x_priv(encoder);
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if (REG2PAGE(reg) != priv->current_page) {
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struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
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struct i2c_client *client = priv->hdmi;
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uint8_t buf[] = {
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REG_CURPAGE, REG2PAGE(reg)
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};
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@ -381,13 +380,13 @@ set_page(struct drm_encoder *encoder, uint16_t reg)
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}
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static int
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reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt)
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reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt)
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{
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struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
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struct i2c_client *client = priv->hdmi;
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uint8_t addr = REG2ADDR(reg);
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int ret;
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set_page(encoder, reg);
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set_page(priv, reg);
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ret = i2c_master_send(client, &addr, sizeof(addr));
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if (ret < 0)
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@ -405,16 +404,16 @@ fail:
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}
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static void
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reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt)
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reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt)
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{
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struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
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struct i2c_client *client = priv->hdmi;
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uint8_t buf[cnt+1];
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int ret;
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buf[0] = REG2ADDR(reg);
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memcpy(&buf[1], p, cnt);
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set_page(encoder, reg);
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set_page(priv, reg);
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ret = i2c_master_send(client, buf, cnt + 1);
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if (ret < 0)
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@ -422,21 +421,21 @@ reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt)
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}
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static uint8_t
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reg_read(struct drm_encoder *encoder, uint16_t reg)
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reg_read(struct tda998x_priv *priv, uint16_t reg)
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{
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uint8_t val = 0;
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reg_read_range(encoder, reg, &val, sizeof(val));
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reg_read_range(priv, reg, &val, sizeof(val));
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return val;
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}
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static void
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reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
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reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
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{
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struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
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struct i2c_client *client = priv->hdmi;
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uint8_t buf[] = {REG2ADDR(reg), val};
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int ret;
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set_page(encoder, reg);
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set_page(priv, reg);
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ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
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if (ret < 0)
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@ -444,13 +443,13 @@ reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
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}
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static void
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reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val)
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reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val)
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{
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struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
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struct i2c_client *client = priv->hdmi;
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uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
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int ret;
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set_page(encoder, reg);
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set_page(priv, reg);
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ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
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if (ret < 0)
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@ -458,47 +457,47 @@ reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val)
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}
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static void
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reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
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reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
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{
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reg_write(encoder, reg, reg_read(encoder, reg) | val);
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reg_write(priv, reg, reg_read(priv, reg) | val);
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}
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static void
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reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
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reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
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{
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reg_write(encoder, reg, reg_read(encoder, reg) & ~val);
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reg_write(priv, reg, reg_read(priv, reg) & ~val);
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}
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static void
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tda998x_reset(struct drm_encoder *encoder)
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tda998x_reset(struct tda998x_priv *priv)
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{
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/* reset audio and i2c master: */
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reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
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reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
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msleep(50);
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reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
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reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
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msleep(50);
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/* reset transmitter: */
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reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
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reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
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reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
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reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
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/* PLL registers common configuration */
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reg_write(encoder, REG_PLL_SERIAL_1, 0x00);
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reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
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reg_write(encoder, REG_PLL_SERIAL_3, 0x00);
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reg_write(encoder, REG_SERIALIZER, 0x00);
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reg_write(encoder, REG_BUFFER_OUT, 0x00);
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reg_write(encoder, REG_PLL_SCG1, 0x00);
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reg_write(encoder, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
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reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
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reg_write(encoder, REG_PLL_SCGN1, 0xfa);
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reg_write(encoder, REG_PLL_SCGN2, 0x00);
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reg_write(encoder, REG_PLL_SCGR1, 0x5b);
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reg_write(encoder, REG_PLL_SCGR2, 0x00);
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reg_write(encoder, REG_PLL_SCG2, 0x10);
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reg_write(priv, REG_PLL_SERIAL_1, 0x00);
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reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
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reg_write(priv, REG_PLL_SERIAL_3, 0x00);
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reg_write(priv, REG_SERIALIZER, 0x00);
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reg_write(priv, REG_BUFFER_OUT, 0x00);
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reg_write(priv, REG_PLL_SCG1, 0x00);
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reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
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reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
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reg_write(priv, REG_PLL_SCGN1, 0xfa);
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reg_write(priv, REG_PLL_SCGN2, 0x00);
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reg_write(priv, REG_PLL_SCGR1, 0x5b);
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reg_write(priv, REG_PLL_SCGR2, 0x00);
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reg_write(priv, REG_PLL_SCG2, 0x10);
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/* Write the default value MUX register */
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reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24);
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reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
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}
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static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
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@ -514,18 +513,18 @@ static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
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#define PB(x) (HB(2) + 1 + (x))
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static void
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tda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr,
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tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
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uint8_t *buf, size_t size)
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{
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buf[PB(0)] = tda998x_cksum(buf, size);
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reg_clear(encoder, REG_DIP_IF_FLAGS, bit);
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reg_write_range(encoder, addr, buf, size);
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reg_set(encoder, REG_DIP_IF_FLAGS, bit);
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reg_clear(priv, REG_DIP_IF_FLAGS, bit);
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reg_write_range(priv, addr, buf, size);
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reg_set(priv, REG_DIP_IF_FLAGS, bit);
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}
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static void
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tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p)
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tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
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{
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u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
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@ -538,12 +537,12 @@ tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p)
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buf[PB(4)] = p->audio_frame[4];
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buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
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tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
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tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
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sizeof(buf));
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}
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static void
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tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode)
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tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
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{
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u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1];
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@ -556,36 +555,36 @@ tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode)
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buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2;
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buf[PB(4)] = drm_match_cea_mode(mode);
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tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
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tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
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sizeof(buf));
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}
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static void tda998x_audio_mute(struct drm_encoder *encoder, bool on)
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static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
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{
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if (on) {
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reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO);
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reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO);
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reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
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reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
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reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
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reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
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} else {
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reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
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reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
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}
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}
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static void
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tda998x_configure_audio(struct drm_encoder *encoder,
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tda998x_configure_audio(struct tda998x_priv *priv,
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struct drm_display_mode *mode, struct tda998x_encoder_params *p)
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{
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uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv;
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uint32_t n;
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/* Enable audio ports */
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reg_write(encoder, REG_ENA_AP, p->audio_cfg);
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reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg);
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reg_write(priv, REG_ENA_AP, p->audio_cfg);
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reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
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/* Set audio input source */
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switch (p->audio_format) {
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case AFMT_SPDIF:
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reg_write(encoder, REG_MUX_AP, 0x40);
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reg_write(priv, REG_MUX_AP, 0x40);
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clksel_aip = AIP_CLKSEL_AIP(0);
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/* FS64SPDIF */
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clksel_fs = AIP_CLKSEL_FS(2);
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@ -594,7 +593,7 @@ tda998x_configure_audio(struct drm_encoder *encoder,
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break;
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case AFMT_I2S:
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reg_write(encoder, REG_MUX_AP, 0x64);
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reg_write(priv, REG_MUX_AP, 0x64);
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clksel_aip = AIP_CLKSEL_AIP(1);
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/* ACLK */
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clksel_fs = AIP_CLKSEL_FS(0);
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@ -607,12 +606,12 @@ tda998x_configure_audio(struct drm_encoder *encoder,
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return;
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}
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reg_write(encoder, REG_AIP_CLKSEL, clksel_aip);
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reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT);
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reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
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reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT);
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/* Enable automatic CTS generation */
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reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN);
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reg_write(encoder, REG_CTS_N, cts_n);
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reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN);
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reg_write(priv, REG_CTS_N, cts_n);
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/*
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* Audio input somehow depends on HDMI line rate which is
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@ -625,7 +624,7 @@ tda998x_configure_audio(struct drm_encoder *encoder,
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adiv = AUDIO_DIV_SERCLK_16;
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else
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adiv = AUDIO_DIV_SERCLK_8;
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reg_write(encoder, REG_AUDIO_DIV, adiv);
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reg_write(priv, REG_AUDIO_DIV, adiv);
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/*
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* This is the approximate value of N, which happens to be
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@ -640,14 +639,14 @@ tda998x_configure_audio(struct drm_encoder *encoder,
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buf[3] = n;
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buf[4] = n >> 8;
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buf[5] = n >> 16;
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reg_write_range(encoder, REG_ACR_CTS_0, buf, 6);
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reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
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/* Set CTS clock reference */
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reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
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reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
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/* Reset CTS generator */
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reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
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reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
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reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
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reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
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/* Write the channel status */
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buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
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@ -655,14 +654,14 @@ tda998x_configure_audio(struct drm_encoder *encoder,
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buf[2] = IEC958_AES3_CON_FS_NOTID;
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buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
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IEC958_AES4_CON_MAX_WORDLEN_24;
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reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4);
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reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
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tda998x_audio_mute(encoder, true);
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tda998x_audio_mute(priv, true);
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mdelay(20);
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tda998x_audio_mute(encoder, false);
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tda998x_audio_mute(priv, false);
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/* Write the audio information packet */
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tda998x_write_aif(encoder, p);
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tda998x_write_aif(priv, p);
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}
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/* DRM encoder functions */
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@ -704,19 +703,19 @@ tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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/* enable video ports, audio will be enabled later */
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reg_write(encoder, REG_ENA_VP_0, 0xff);
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reg_write(encoder, REG_ENA_VP_1, 0xff);
|
||||
reg_write(encoder, REG_ENA_VP_2, 0xff);
|
||||
reg_write(priv, REG_ENA_VP_0, 0xff);
|
||||
reg_write(priv, REG_ENA_VP_1, 0xff);
|
||||
reg_write(priv, REG_ENA_VP_2, 0xff);
|
||||
/* set muxing after enabling ports: */
|
||||
reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
|
||||
reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
|
||||
reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
|
||||
reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
|
||||
reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
|
||||
reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
|
||||
break;
|
||||
case DRM_MODE_DPMS_OFF:
|
||||
/* disable video ports */
|
||||
reg_write(encoder, REG_ENA_VP_0, 0x00);
|
||||
reg_write(encoder, REG_ENA_VP_1, 0x00);
|
||||
reg_write(encoder, REG_ENA_VP_2, 0x00);
|
||||
reg_write(priv, REG_ENA_VP_0, 0x00);
|
||||
reg_write(priv, REG_ENA_VP_1, 0x00);
|
||||
reg_write(priv, REG_ENA_VP_2, 0x00);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -834,57 +833,57 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
|
||||
}
|
||||
|
||||
/* mute the audio FIFO: */
|
||||
reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
|
||||
reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
|
||||
|
||||
/* set HDMI HDCP mode off: */
|
||||
reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
|
||||
reg_clear(encoder, REG_TX33, TX33_HDMI);
|
||||
reg_set(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
|
||||
reg_clear(priv, REG_TX33, TX33_HDMI);
|
||||
reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
|
||||
|
||||
reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
|
||||
/* no pre-filter or interpolator: */
|
||||
reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
|
||||
reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
|
||||
HVF_CNTRL_0_INTPOL(0));
|
||||
reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
|
||||
reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
|
||||
reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
|
||||
reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
|
||||
VIP_CNTRL_4_BLC(0));
|
||||
reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR);
|
||||
reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR);
|
||||
|
||||
reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
|
||||
reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE);
|
||||
reg_write(encoder, REG_SERIALIZER, 0);
|
||||
reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
|
||||
reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
|
||||
reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE);
|
||||
reg_write(priv, REG_SERIALIZER, 0);
|
||||
reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
|
||||
|
||||
/* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
|
||||
rep = 0;
|
||||
reg_write(encoder, REG_RPT_CNTRL, 0);
|
||||
reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
|
||||
reg_write(priv, REG_RPT_CNTRL, 0);
|
||||
reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
|
||||
SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
|
||||
|
||||
reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
|
||||
reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
|
||||
PLL_SERIAL_2_SRL_PR(rep));
|
||||
|
||||
/* set color matrix bypass flag: */
|
||||
reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP);
|
||||
reg_set(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP);
|
||||
|
||||
/* set BIAS tmds value: */
|
||||
reg_write(encoder, REG_ANA_GENERAL, 0x09);
|
||||
reg_write(priv, REG_ANA_GENERAL, 0x09);
|
||||
|
||||
reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD);
|
||||
reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD);
|
||||
|
||||
/*
|
||||
* Sync on rising HSYNC/VSYNC
|
||||
*/
|
||||
reg_write(encoder, REG_VIP_CNTRL_3, 0);
|
||||
reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS);
|
||||
reg_write(priv, REG_VIP_CNTRL_3, 0);
|
||||
reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS);
|
||||
|
||||
/*
|
||||
* TDA19988 requires high-active sync at input stage,
|
||||
* so invert low-active sync provided by master encoder here
|
||||
*/
|
||||
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
|
||||
reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
|
||||
reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
|
||||
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
|
||||
reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL);
|
||||
reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL);
|
||||
|
||||
/*
|
||||
* Always generate sync polarity relative to input sync and
|
||||
@ -895,49 +894,49 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
|
||||
reg |= TBG_CNTRL_1_H_TGL;
|
||||
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
|
||||
reg |= TBG_CNTRL_1_V_TGL;
|
||||
reg_write(encoder, REG_TBG_CNTRL_1, reg);
|
||||
reg_write(priv, REG_TBG_CNTRL_1, reg);
|
||||
|
||||
reg_write(encoder, REG_VIDFORMAT, 0x00);
|
||||
reg_write16(encoder, REG_REFPIX_MSB, ref_pix);
|
||||
reg_write16(encoder, REG_REFLINE_MSB, ref_line);
|
||||
reg_write16(encoder, REG_NPIX_MSB, n_pix);
|
||||
reg_write16(encoder, REG_NLINE_MSB, n_line);
|
||||
reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
|
||||
reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
|
||||
reg_write16(encoder, REG_VS_LINE_END_1_MSB, vs1_line_e);
|
||||
reg_write16(encoder, REG_VS_PIX_END_1_MSB, vs1_pix_e);
|
||||
reg_write16(encoder, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
|
||||
reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
|
||||
reg_write16(encoder, REG_VS_LINE_END_2_MSB, vs2_line_e);
|
||||
reg_write16(encoder, REG_VS_PIX_END_2_MSB, vs2_pix_e);
|
||||
reg_write16(encoder, REG_HS_PIX_START_MSB, hs_pix_s);
|
||||
reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_pix_e);
|
||||
reg_write16(encoder, REG_VWIN_START_1_MSB, vwin1_line_s);
|
||||
reg_write16(encoder, REG_VWIN_END_1_MSB, vwin1_line_e);
|
||||
reg_write16(encoder, REG_VWIN_START_2_MSB, vwin2_line_s);
|
||||
reg_write16(encoder, REG_VWIN_END_2_MSB, vwin2_line_e);
|
||||
reg_write16(encoder, REG_DE_START_MSB, de_pix_s);
|
||||
reg_write16(encoder, REG_DE_STOP_MSB, de_pix_e);
|
||||
reg_write(priv, REG_VIDFORMAT, 0x00);
|
||||
reg_write16(priv, REG_REFPIX_MSB, ref_pix);
|
||||
reg_write16(priv, REG_REFLINE_MSB, ref_line);
|
||||
reg_write16(priv, REG_NPIX_MSB, n_pix);
|
||||
reg_write16(priv, REG_NLINE_MSB, n_line);
|
||||
reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
|
||||
reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
|
||||
reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
|
||||
reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
|
||||
reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
|
||||
reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
|
||||
reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
|
||||
reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
|
||||
reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
|
||||
reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
|
||||
reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
|
||||
reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
|
||||
reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
|
||||
reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
|
||||
reg_write16(priv, REG_DE_START_MSB, de_pix_s);
|
||||
reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
|
||||
|
||||
if (priv->rev == TDA19988) {
|
||||
/* let incoming pixels fill the active space (if any) */
|
||||
reg_write(encoder, REG_ENABLE_SPACE, 0x00);
|
||||
reg_write(priv, REG_ENABLE_SPACE, 0x00);
|
||||
}
|
||||
|
||||
/* must be last register set: */
|
||||
reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
|
||||
reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
|
||||
|
||||
/* Only setup the info frames if the sink is HDMI */
|
||||
if (priv->is_hdmi_sink) {
|
||||
/* We need to turn HDMI HDCP stuff on to get audio through */
|
||||
reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
|
||||
reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
|
||||
reg_set(encoder, REG_TX33, TX33_HDMI);
|
||||
reg_clear(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
|
||||
reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
|
||||
reg_set(priv, REG_TX33, TX33_HDMI);
|
||||
|
||||
tda998x_write_avi(encoder, adjusted_mode);
|
||||
tda998x_write_avi(priv, adjusted_mode);
|
||||
|
||||
if (priv->params.audio_cfg)
|
||||
tda998x_configure_audio(encoder, adjusted_mode,
|
||||
tda998x_configure_audio(priv, adjusted_mode,
|
||||
&priv->params);
|
||||
}
|
||||
}
|
||||
@ -946,7 +945,9 @@ static enum drm_connector_status
|
||||
tda998x_encoder_detect(struct drm_encoder *encoder,
|
||||
struct drm_connector *connector)
|
||||
{
|
||||
uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV);
|
||||
struct tda998x_priv *priv = to_tda998x_priv(encoder);
|
||||
uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV);
|
||||
|
||||
return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
|
||||
connector_status_disconnected;
|
||||
}
|
||||
@ -954,29 +955,30 @@ tda998x_encoder_detect(struct drm_encoder *encoder,
|
||||
static int
|
||||
read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
|
||||
{
|
||||
struct tda998x_priv *priv = to_tda998x_priv(encoder);
|
||||
uint8_t offset, segptr;
|
||||
int ret, i;
|
||||
|
||||
/* enable EDID read irq: */
|
||||
reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
|
||||
reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
|
||||
|
||||
offset = (blk & 1) ? 128 : 0;
|
||||
segptr = blk / 2;
|
||||
|
||||
reg_write(encoder, REG_DDC_ADDR, 0xa0);
|
||||
reg_write(encoder, REG_DDC_OFFS, offset);
|
||||
reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60);
|
||||
reg_write(encoder, REG_DDC_SEGM, segptr);
|
||||
reg_write(priv, REG_DDC_ADDR, 0xa0);
|
||||
reg_write(priv, REG_DDC_OFFS, offset);
|
||||
reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
|
||||
reg_write(priv, REG_DDC_SEGM, segptr);
|
||||
|
||||
/* enable reading EDID: */
|
||||
reg_write(encoder, REG_EDID_CTRL, 0x1);
|
||||
reg_write(priv, REG_EDID_CTRL, 0x1);
|
||||
|
||||
/* flag must be cleared by sw: */
|
||||
reg_write(encoder, REG_EDID_CTRL, 0x0);
|
||||
reg_write(priv, REG_EDID_CTRL, 0x0);
|
||||
|
||||
/* wait for block read to complete: */
|
||||
for (i = 100; i > 0; i--) {
|
||||
uint8_t val = reg_read(encoder, REG_INT_FLAGS_2);
|
||||
uint8_t val = reg_read(priv, REG_INT_FLAGS_2);
|
||||
if (val & INT_FLAGS_2_EDID_BLK_RD)
|
||||
break;
|
||||
msleep(1);
|
||||
@ -985,14 +987,14 @@ read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
|
||||
if (i == 0)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH);
|
||||
ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH);
|
||||
if (ret != EDID_LENGTH) {
|
||||
dev_err(encoder->dev->dev, "failed to read edid block %d: %d",
|
||||
blk, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
|
||||
reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1009,7 +1011,7 @@ do_get_edid(struct drm_encoder *encoder)
|
||||
return NULL;
|
||||
|
||||
if (priv->rev == TDA19988)
|
||||
reg_clear(encoder, REG_TX4, TX4_PD_RAM);
|
||||
reg_clear(priv, REG_TX4, TX4_PD_RAM);
|
||||
|
||||
/* base block fetch */
|
||||
if (read_edid_block(encoder, block, 0))
|
||||
@ -1049,13 +1051,13 @@ do_get_edid(struct drm_encoder *encoder)
|
||||
|
||||
done:
|
||||
if (priv->rev == TDA19988)
|
||||
reg_set(encoder, REG_TX4, TX4_PD_RAM);
|
||||
reg_set(priv, REG_TX4, TX4_PD_RAM);
|
||||
|
||||
return block;
|
||||
|
||||
fail:
|
||||
if (priv->rev == TDA19988)
|
||||
reg_set(encoder, REG_TX4, TX4_PD_RAM);
|
||||
reg_set(priv, REG_TX4, TX4_PD_RAM);
|
||||
dev_warn(encoder->dev->dev, "failed to read EDID\n");
|
||||
kfree(block);
|
||||
return NULL;
|
||||
@ -1141,7 +1143,6 @@ tda998x_encoder_init(struct i2c_client *client,
|
||||
struct drm_device *dev,
|
||||
struct drm_encoder_slave *encoder_slave)
|
||||
{
|
||||
struct drm_encoder *encoder = &encoder_slave->base;
|
||||
struct tda998x_priv *priv;
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
@ -1153,6 +1154,7 @@ tda998x_encoder_init(struct i2c_client *client,
|
||||
priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
|
||||
|
||||
priv->current_page = 0xff;
|
||||
priv->hdmi = client;
|
||||
priv->cec = i2c_new_dummy(client->adapter, 0x34);
|
||||
if (!priv->cec) {
|
||||
kfree(priv);
|
||||
@ -1164,14 +1166,14 @@ tda998x_encoder_init(struct i2c_client *client,
|
||||
encoder_slave->slave_funcs = &tda998x_encoder_funcs;
|
||||
|
||||
/* wake up the device: */
|
||||
cec_write(encoder, REG_CEC_ENAMODS,
|
||||
cec_write(priv, REG_CEC_ENAMODS,
|
||||
CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
|
||||
|
||||
tda998x_reset(encoder);
|
||||
tda998x_reset(priv);
|
||||
|
||||
/* read version: */
|
||||
priv->rev = reg_read(encoder, REG_VERSION_LSB) |
|
||||
reg_read(encoder, REG_VERSION_MSB) << 8;
|
||||
priv->rev = reg_read(priv, REG_VERSION_LSB) |
|
||||
reg_read(priv, REG_VERSION_MSB) << 8;
|
||||
|
||||
/* mask off feature bits: */
|
||||
priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
|
||||
@ -1187,16 +1189,16 @@ tda998x_encoder_init(struct i2c_client *client,
|
||||
}
|
||||
|
||||
/* after reset, enable DDC: */
|
||||
reg_write(encoder, REG_DDC_DISABLE, 0x00);
|
||||
reg_write(priv, REG_DDC_DISABLE, 0x00);
|
||||
|
||||
/* set clock on DDC channel: */
|
||||
reg_write(encoder, REG_TX3, 39);
|
||||
reg_write(priv, REG_TX3, 39);
|
||||
|
||||
/* if necessary, disable multi-master: */
|
||||
if (priv->rev == TDA19989)
|
||||
reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
|
||||
reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
|
||||
|
||||
cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL,
|
||||
cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
|
||||
CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
|
||||
|
||||
return 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user