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clk: stm32: Add DSI clock for STM32F469 Board
This patch adds DSI clock for STM32F469 board Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -521,7 +521,7 @@ static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
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};
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static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
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{ PLL, 50, { "pll", "pll-q", NULL } },
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{ PLL, 50, { "pll", "pll-q", "pll-r" } },
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{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
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{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
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};
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@ -1047,6 +1047,8 @@ static const char *rtc_parents[4] = {
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"no-clock", "lse", "lsi", "hse-rtc"
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};
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static const char *dsi_parent[2] = { NULL, "pll-r" };
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static const char *lcd_parent[1] = { "pllsai-r-div" };
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static const char *i2s_parents[2] = { "plli2s-r", NULL };
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@ -1156,6 +1158,12 @@ static const struct stm32_aux_clk stm32f469_aux_clk[] = {
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NO_GATE, 0,
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0
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},
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{
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CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
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STM32F4_RCC_DCKCFGR, 29, 1,
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STM32F4_RCC_APB2ENR, 27,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
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},
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};
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static const struct stm32_aux_clk stm32f746_aux_clk[] = {
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@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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stm32f4_gate_map = data->gates_map;
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hse_clk = of_clk_get_parent_name(np, 0);
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dsi_parent[0] = hse_clk;
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i2s_in_clk = of_clk_get_parent_name(np, 1);
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@ -35,8 +35,9 @@
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#define CLK_SAIQ_PDIV 13
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#define CLK_HSI 14
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#define CLK_SYSCLK 15
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#define CLK_F469_DSI 16
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#define END_PRIMARY_CLK 16
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#define END_PRIMARY_CLK 17
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#define CLK_HDMI_CEC 16
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#define CLK_SPDIF 17
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