mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 11:44:01 +08:00
Merge branch 'for-2.6.37' of git://git.kernel.org/pub/scm/linux/kernel/git/lrg/asoc-2.6 into for-2.6.37
This commit is contained in:
Mark Brown
commit
2f02a59c55
@ -710,10 +710,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
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.vio = &rx51_vio,
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};
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static struct aic3x_pdata rx51_aic3x_data __initdata = {
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.gpio_reset = 60,
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};
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static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = {
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.id = TPA6130A2,
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.power_gpio = 98,
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@ -292,64 +292,102 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = {
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SOC_DOUBLE_R_TLV("PCM Playback Volume",
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LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
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/*
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* Output controls that map to output mixer switches. Note these are
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* only for swapped L-to-R and R-to-L routes. See below stereo controls
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* for direct L-to-L and R-to-R routes.
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*/
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SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
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LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
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PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
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DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
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LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
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PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
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DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
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LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
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PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
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DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
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LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
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PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
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DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
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LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
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PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
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DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
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LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
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PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
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DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
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/* Stereo output controls for direct L-to-L and R-to-R routes */
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SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
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LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
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PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
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DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
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SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
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SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
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DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
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PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
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PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
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LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
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LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
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LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
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PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
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DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
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SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
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PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
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LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
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LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
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PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
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DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
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0x01, 0),
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SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
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PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
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PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
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PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
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LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
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LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
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PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
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DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
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0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
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/* Output pin mute controls */
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SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
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0x01, 0),
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SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
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SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
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0x01, 0),
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SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
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0x01, 0),
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SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
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PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
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PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
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SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
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LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
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0, 118, 1, output_stage_tlv),
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/*
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* Note: enable Automatic input Gain Controller with care. It can
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@ -389,22 +427,74 @@ SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
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static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
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SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
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/* Left DAC_L1 Mixer */
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static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
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SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
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/* Left Line Mixer */
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static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
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SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
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};
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/* Right DAC_R1 Mixer */
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static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
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SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
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/* Right Line Mixer */
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static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
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SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
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};
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/* Mono Mixer */
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static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
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SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
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};
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/* Left HP Mixer */
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static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
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SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
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};
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/* Right HP Mixer */
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static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
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SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
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};
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/* Left HPCOM Mixer */
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static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
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SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
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};
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/* Right HPCOM Mixer */
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static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
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SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
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};
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/* Left PGA Mixer */
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@ -441,54 +531,11 @@ SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
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static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
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SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
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/* Left PGA Bypass Mixer */
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static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
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SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
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};
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/* Right PGA Bypass Mixer */
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static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
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SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
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};
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/* Left Line2 Bypass Mixer */
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static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
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SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
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SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
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};
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/* Right Line2 Bypass Mixer */
|
||||
static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
|
||||
SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
|
||||
SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
|
||||
SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
|
||||
SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
|
||||
SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
|
||||
/* Left DAC to Left Outputs */
|
||||
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
|
||||
SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_left_dac_mux_controls),
|
||||
SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_left_dac_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
|
||||
SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_left_hpcom_mux_controls),
|
||||
SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
|
||||
@ -499,9 +546,6 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
|
||||
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
|
||||
SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_right_dac_mux_controls),
|
||||
SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_right_dac_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
|
||||
SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_right_hpcom_mux_controls),
|
||||
SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
|
||||
@ -565,25 +609,28 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
|
||||
SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
|
||||
MICBIAS_CTRL, 6, 3, 3, 0),
|
||||
|
||||
/* Left PGA to Left Output bypass */
|
||||
SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_left_pga_bp_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
|
||||
|
||||
/* Right PGA to Right Output bypass */
|
||||
SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_right_pga_bp_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
|
||||
|
||||
/* Left Line2 to Left Output bypass */
|
||||
SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_left_line2_bp_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
|
||||
|
||||
/* Right Line2 to Right Output bypass */
|
||||
SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_right_line2_bp_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
|
||||
/* Output mixers */
|
||||
SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_left_line_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_left_line_mixer_controls)),
|
||||
SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_right_line_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_right_line_mixer_controls)),
|
||||
SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_mono_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_mono_mixer_controls)),
|
||||
SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_left_hp_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
|
||||
SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_right_hp_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
|
||||
SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_left_hpcom_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
|
||||
SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
|
||||
&aic3x_right_hpcom_mixer_controls[0],
|
||||
ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
|
||||
|
||||
SND_SOC_DAPM_OUTPUT("LLOUT"),
|
||||
SND_SOC_DAPM_OUTPUT("RLOUT"),
|
||||
@ -611,66 +658,6 @@ static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route intercon[] = {
|
||||
/* Left Output */
|
||||
{"Left DAC Mux", "DAC_L1", "Left DAC"},
|
||||
{"Left DAC Mux", "DAC_L2", "Left DAC"},
|
||||
{"Left DAC Mux", "DAC_L3", "Left DAC"},
|
||||
|
||||
{"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
|
||||
{"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
|
||||
{"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
|
||||
{"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
|
||||
{"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
|
||||
{"Left Line Out", NULL, "Left DAC Mux"},
|
||||
{"Left HP Out", NULL, "Left DAC Mux"},
|
||||
|
||||
{"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
|
||||
{"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
|
||||
{"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
|
||||
|
||||
{"Left Line Out", NULL, "Left DAC_L1 Mixer"},
|
||||
{"Mono Out", NULL, "Left DAC_L1 Mixer"},
|
||||
{"Left HP Out", NULL, "Left DAC_L1 Mixer"},
|
||||
{"Left HP Com", NULL, "Left HPCOM Mux"},
|
||||
|
||||
{"LLOUT", NULL, "Left Line Out"},
|
||||
{"LLOUT", NULL, "Left Line Out"},
|
||||
{"HPLOUT", NULL, "Left HP Out"},
|
||||
{"HPLCOM", NULL, "Left HP Com"},
|
||||
|
||||
/* Right Output */
|
||||
{"Right DAC Mux", "DAC_R1", "Right DAC"},
|
||||
{"Right DAC Mux", "DAC_R2", "Right DAC"},
|
||||
{"Right DAC Mux", "DAC_R3", "Right DAC"},
|
||||
|
||||
{"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
|
||||
{"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
|
||||
{"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
|
||||
{"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
|
||||
{"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
|
||||
{"Right Line Out", NULL, "Right DAC Mux"},
|
||||
{"Right HP Out", NULL, "Right DAC Mux"},
|
||||
|
||||
{"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
|
||||
{"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
|
||||
{"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
|
||||
{"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
|
||||
{"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
|
||||
|
||||
{"Right Line Out", NULL, "Right DAC_R1 Mixer"},
|
||||
{"Mono Out", NULL, "Right DAC_R1 Mixer"},
|
||||
{"Right HP Out", NULL, "Right DAC_R1 Mixer"},
|
||||
{"Right HP Com", NULL, "Right HPCOM Mux"},
|
||||
|
||||
{"RLOUT", NULL, "Right Line Out"},
|
||||
{"RLOUT", NULL, "Right Line Out"},
|
||||
{"HPROUT", NULL, "Right HP Out"},
|
||||
{"HPRCOM", NULL, "Right HP Com"},
|
||||
|
||||
/* Mono Output */
|
||||
{"MONO_LOUT", NULL, "Mono Out"},
|
||||
{"MONO_LOUT", NULL, "Mono Out"},
|
||||
|
||||
/* Left Input */
|
||||
{"Left Line1L Mux", "single-ended", "LINE1L"},
|
||||
{"Left Line1L Mux", "differential", "LINE1L"},
|
||||
@ -703,74 +690,6 @@ static const struct snd_soc_dapm_route intercon[] = {
|
||||
{"Right ADC", NULL, "Right PGA Mixer"},
|
||||
{"Right ADC", NULL, "GPIO1 dmic modclk"},
|
||||
|
||||
/* Left PGA Bypass */
|
||||
{"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
|
||||
{"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
|
||||
{"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
|
||||
{"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
|
||||
{"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
|
||||
{"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
|
||||
{"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
|
||||
|
||||
{"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
|
||||
{"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
|
||||
{"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
|
||||
|
||||
{"Left Line Out", NULL, "Left PGA Bypass Mixer"},
|
||||
{"Mono Out", NULL, "Left PGA Bypass Mixer"},
|
||||
{"Left HP Out", NULL, "Left PGA Bypass Mixer"},
|
||||
|
||||
/* Right PGA Bypass */
|
||||
{"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
|
||||
{"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
|
||||
{"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
|
||||
{"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
|
||||
{"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
|
||||
{"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
|
||||
{"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
|
||||
|
||||
{"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
|
||||
{"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
|
||||
{"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
|
||||
{"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
|
||||
{"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
|
||||
|
||||
{"Right Line Out", NULL, "Right PGA Bypass Mixer"},
|
||||
{"Mono Out", NULL, "Right PGA Bypass Mixer"},
|
||||
{"Right HP Out", NULL, "Right PGA Bypass Mixer"},
|
||||
|
||||
/* Left Line2 Bypass */
|
||||
{"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
|
||||
{"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
|
||||
{"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
|
||||
{"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
|
||||
{"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
|
||||
|
||||
{"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
|
||||
{"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
|
||||
{"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
|
||||
|
||||
{"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
|
||||
{"Mono Out", NULL, "Left Line2 Bypass Mixer"},
|
||||
{"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
|
||||
|
||||
/* Right Line2 Bypass */
|
||||
{"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
|
||||
{"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
|
||||
{"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
|
||||
{"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
|
||||
{"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
|
||||
|
||||
{"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
|
||||
{"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
|
||||
{"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
|
||||
{"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
|
||||
{"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
|
||||
|
||||
{"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
|
||||
{"Mono Out", NULL, "Right Line2 Bypass Mixer"},
|
||||
{"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
|
||||
|
||||
/*
|
||||
* Logical path between digital mic enable and GPIO1 modulator clock
|
||||
* output function
|
||||
@ -778,6 +697,105 @@ static const struct snd_soc_dapm_route intercon[] = {
|
||||
{"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
|
||||
{"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
|
||||
{"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
|
||||
|
||||
/* Left DAC Output */
|
||||
{"Left DAC Mux", "DAC_L1", "Left DAC"},
|
||||
{"Left DAC Mux", "DAC_L2", "Left DAC"},
|
||||
{"Left DAC Mux", "DAC_L3", "Left DAC"},
|
||||
|
||||
/* Right DAC Output */
|
||||
{"Right DAC Mux", "DAC_R1", "Right DAC"},
|
||||
{"Right DAC Mux", "DAC_R2", "Right DAC"},
|
||||
{"Right DAC Mux", "DAC_R3", "Right DAC"},
|
||||
|
||||
/* Left Line Output */
|
||||
{"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
|
||||
{"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
|
||||
{"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
|
||||
{"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
|
||||
{"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
|
||||
{"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
|
||||
|
||||
{"Left Line Out", NULL, "Left Line Mixer"},
|
||||
{"Left Line Out", NULL, "Left DAC Mux"},
|
||||
{"LLOUT", NULL, "Left Line Out"},
|
||||
|
||||
/* Right Line Output */
|
||||
{"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
|
||||
{"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
|
||||
{"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
|
||||
{"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
|
||||
{"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
|
||||
{"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
|
||||
|
||||
{"Right Line Out", NULL, "Right Line Mixer"},
|
||||
{"Right Line Out", NULL, "Right DAC Mux"},
|
||||
{"RLOUT", NULL, "Right Line Out"},
|
||||
|
||||
/* Mono Output */
|
||||
{"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
|
||||
{"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
|
||||
{"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
|
||||
{"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
|
||||
{"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
|
||||
{"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
|
||||
|
||||
{"Mono Out", NULL, "Mono Mixer"},
|
||||
{"MONO_LOUT", NULL, "Mono Out"},
|
||||
|
||||
/* Left HP Output */
|
||||
{"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
|
||||
{"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
|
||||
{"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
|
||||
{"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
|
||||
{"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
|
||||
{"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
|
||||
|
||||
{"Left HP Out", NULL, "Left HP Mixer"},
|
||||
{"Left HP Out", NULL, "Left DAC Mux"},
|
||||
{"HPLOUT", NULL, "Left HP Out"},
|
||||
|
||||
/* Right HP Output */
|
||||
{"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
|
||||
{"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
|
||||
{"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
|
||||
{"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
|
||||
{"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
|
||||
{"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
|
||||
|
||||
{"Right HP Out", NULL, "Right HP Mixer"},
|
||||
{"Right HP Out", NULL, "Right DAC Mux"},
|
||||
{"HPROUT", NULL, "Right HP Out"},
|
||||
|
||||
/* Left HPCOM Output */
|
||||
{"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
|
||||
{"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
|
||||
{"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
|
||||
{"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
|
||||
{"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
|
||||
{"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
|
||||
|
||||
{"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
|
||||
{"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
|
||||
{"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
|
||||
{"Left HP Com", NULL, "Left HPCOM Mux"},
|
||||
{"HPLCOM", NULL, "Left HP Com"},
|
||||
|
||||
/* Right HPCOM Output */
|
||||
{"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
|
||||
{"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
|
||||
{"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
|
||||
{"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
|
||||
{"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
|
||||
{"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
|
||||
|
||||
{"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
|
||||
{"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
|
||||
{"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
|
||||
{"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
|
||||
{"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
|
||||
{"Right HP Com", NULL, "Right HPCOM Mux"},
|
||||
{"HPRCOM", NULL, "Right HP Com"},
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route intercon_3007[] = {
|
||||
@ -1281,6 +1299,8 @@ static int aic3x_probe(struct snd_soc_codec *codec)
|
||||
codec->hw_write = (hw_write_t) i2c_master_send;
|
||||
codec->control_data = aic3x->control_data;
|
||||
|
||||
aic3x_init(codec);
|
||||
|
||||
if (aic3x->setup) {
|
||||
/* setup GPIO functions */
|
||||
aic3x_write(codec, AIC3X_GPIO1_REG,
|
||||
@ -1289,8 +1309,6 @@ static int aic3x_probe(struct snd_soc_codec *codec)
|
||||
(aic3x->setup->gpio_func[1] & 0xf) << 4);
|
||||
}
|
||||
|
||||
aic3x_init(codec);
|
||||
|
||||
snd_soc_add_controls(codec, aic3x_snd_controls,
|
||||
ARRAY_SIZE(aic3x_snd_controls));
|
||||
if (aic3x->model == AIC3X_MODEL_3007)
|
||||
@ -1342,7 +1360,6 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct aic3x_pdata *pdata = i2c->dev.platform_data;
|
||||
struct aic3x_setup_data *setup = pdata->setup;
|
||||
struct aic3x_priv *aic3x;
|
||||
int ret, i;
|
||||
const struct i2c_device_id *tbl;
|
||||
@ -1354,15 +1371,18 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
|
||||
}
|
||||
|
||||
aic3x->control_data = i2c;
|
||||
aic3x->setup = setup;
|
||||
i2c_set_clientdata(i2c, aic3x);
|
||||
if (pdata) {
|
||||
aic3x->gpio_reset = pdata->gpio_reset;
|
||||
aic3x->setup = pdata->setup;
|
||||
} else {
|
||||
aic3x->gpio_reset = -1;
|
||||
}
|
||||
|
||||
aic3x->gpio_reset = -1;
|
||||
if (pdata && pdata->gpio_reset >= 0) {
|
||||
ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset");
|
||||
if (aic3x->gpio_reset >= 0) {
|
||||
ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
|
||||
if (ret != 0)
|
||||
goto err_gpio;
|
||||
aic3x->gpio_reset = pdata->gpio_reset;
|
||||
gpio_direction_output(aic3x->gpio_reset, 0);
|
||||
}
|
||||
|
||||
|
||||
@ -81,52 +81,63 @@
|
||||
/* DAC Digital control registers */
|
||||
#define LDAC_VOL 43
|
||||
#define RDAC_VOL 44
|
||||
/* High Power Output control registers */
|
||||
/* Left High Power Output control registers */
|
||||
#define LINE2L_2_HPLOUT_VOL 45
|
||||
#define LINE2R_2_HPROUT_VOL 62
|
||||
#define PGAL_2_HPLOUT_VOL 46
|
||||
#define PGAL_2_HPROUT_VOL 60
|
||||
#define PGAR_2_HPLOUT_VOL 49
|
||||
#define PGAR_2_HPROUT_VOL 63
|
||||
#define DACL1_2_HPLOUT_VOL 47
|
||||
#define DACR1_2_HPROUT_VOL 64
|
||||
#define LINE2R_2_HPLOUT_VOL 48
|
||||
#define PGAR_2_HPLOUT_VOL 49
|
||||
#define DACR1_2_HPLOUT_VOL 50
|
||||
#define HPLOUT_CTRL 51
|
||||
#define HPROUT_CTRL 65
|
||||
/* High Power COM control registers */
|
||||
/* Left High Power COM control registers */
|
||||
#define LINE2L_2_HPLCOM_VOL 52
|
||||
#define LINE2R_2_HPRCOM_VOL 69
|
||||
#define PGAL_2_HPLCOM_VOL 53
|
||||
#define PGAR_2_HPLCOM_VOL 56
|
||||
#define PGAL_2_HPRCOM_VOL 67
|
||||
#define PGAR_2_HPRCOM_VOL 70
|
||||
#define DACL1_2_HPLCOM_VOL 54
|
||||
#define DACR1_2_HPRCOM_VOL 71
|
||||
#define LINE2R_2_HPLCOM_VOL 55
|
||||
#define PGAR_2_HPLCOM_VOL 56
|
||||
#define DACR1_2_HPLCOM_VOL 57
|
||||
#define HPLCOM_CTRL 58
|
||||
/* Right High Power Output control registers */
|
||||
#define LINE2L_2_HPROUT_VOL 59
|
||||
#define PGAL_2_HPROUT_VOL 60
|
||||
#define DACL1_2_HPROUT_VOL 61
|
||||
#define LINE2R_2_HPROUT_VOL 62
|
||||
#define PGAR_2_HPROUT_VOL 63
|
||||
#define DACR1_2_HPROUT_VOL 64
|
||||
#define HPROUT_CTRL 65
|
||||
/* Right High Power COM control registers */
|
||||
#define LINE2L_2_HPRCOM_VOL 66
|
||||
#define PGAL_2_HPRCOM_VOL 67
|
||||
#define DACL1_2_HPRCOM_VOL 68
|
||||
#define LINE2R_2_HPRCOM_VOL 69
|
||||
#define PGAR_2_HPRCOM_VOL 70
|
||||
#define DACR1_2_HPRCOM_VOL 71
|
||||
#define HPRCOM_CTRL 72
|
||||
/* Mono Line Output Plus/Minus control registers */
|
||||
#define LINE2L_2_MONOLOPM_VOL 73
|
||||
#define LINE2R_2_MONOLOPM_VOL 76
|
||||
#define PGAL_2_MONOLOPM_VOL 74
|
||||
#define PGAR_2_MONOLOPM_VOL 77
|
||||
#define DACL1_2_MONOLOPM_VOL 75
|
||||
#define LINE2R_2_MONOLOPM_VOL 76
|
||||
#define PGAR_2_MONOLOPM_VOL 77
|
||||
#define DACR1_2_MONOLOPM_VOL 78
|
||||
#define MONOLOPM_CTRL 79
|
||||
/* Class-D speaker driver on tlv320aic3007 */
|
||||
#define CLASSD_CTRL 73
|
||||
/* Line Output Plus/Minus control registers */
|
||||
/* Left Line Output Plus/Minus control registers */
|
||||
#define LINE2L_2_LLOPM_VOL 80
|
||||
#define LINE2L_2_RLOPM_VOL 87
|
||||
#define LINE2R_2_LLOPM_VOL 83
|
||||
#define LINE2R_2_RLOPM_VOL 90
|
||||
#define PGAL_2_LLOPM_VOL 81
|
||||
#define PGAL_2_RLOPM_VOL 88
|
||||
#define PGAR_2_LLOPM_VOL 84
|
||||
#define PGAR_2_RLOPM_VOL 91
|
||||
#define DACL1_2_LLOPM_VOL 82
|
||||
#define DACL1_2_RLOPM_VOL 89
|
||||
#define DACR1_2_RLOPM_VOL 92
|
||||
#define LINE2R_2_LLOPM_VOL 83
|
||||
#define PGAR_2_LLOPM_VOL 84
|
||||
#define DACR1_2_LLOPM_VOL 85
|
||||
#define LLOPM_CTRL 86
|
||||
/* Right Line Output Plus/Minus control registers */
|
||||
#define LINE2L_2_RLOPM_VOL 87
|
||||
#define PGAL_2_RLOPM_VOL 88
|
||||
#define DACL1_2_RLOPM_VOL 89
|
||||
#define LINE2R_2_RLOPM_VOL 90
|
||||
#define PGAR_2_RLOPM_VOL 91
|
||||
#define DACR1_2_RLOPM_VOL 92
|
||||
#define RLOPM_CTRL 93
|
||||
/* GPIO/IRQ registers */
|
||||
#define AIC3X_STICKY_IRQ_FLAGS_REG 96
|
||||
|
||||
@ -146,9 +146,9 @@ static int rx51_spk_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *k, int event)
|
||||
{
|
||||
if (SND_SOC_DAPM_EVENT_ON(event))
|
||||
gpio_set_value(RX51_SPEAKER_AMP_TWL_GPIO, 1);
|
||||
gpio_set_value_cansleep(RX51_SPEAKER_AMP_TWL_GPIO, 1);
|
||||
else
|
||||
gpio_set_value(RX51_SPEAKER_AMP_TWL_GPIO, 0);
|
||||
gpio_set_value_cansleep(RX51_SPEAKER_AMP_TWL_GPIO, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user