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clk: samsung: exynos5433: Add clocks for CMU_AUD domain
This patch adds the mux/divider/gate clocks for CMU_AUD domain which includes the clocks of Cortex-A5/Bus/Audio clocks. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
Sylwester Nawrocki
parent
2a1808a6c0
commit
2e997c0359
@ -2459,3 +2459,175 @@ static void __init exynos5433_cmu_disp_init(struct device_node *np)
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CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
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exynos5433_cmu_disp_init);
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/*
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* Register offset definitions for CMU_AUD
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*/
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#define MUX_SEL_AUD0 0x0200
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#define MUX_SEL_AUD1 0x0204
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#define MUX_ENABLE_AUD0 0x0300
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#define MUX_ENABLE_AUD1 0x0304
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#define MUX_STAT_AUD0 0x0400
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#define DIV_AUD0 0x0600
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#define DIV_AUD1 0x0604
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#define DIV_STAT_AUD0 0x0700
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#define DIV_STAT_AUD1 0x0704
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#define ENABLE_ACLK_AUD 0x0800
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#define ENABLE_PCLK_AUD 0x0900
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#define ENABLE_SCLK_AUD0 0x0a00
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#define ENABLE_SCLK_AUD1 0x0a04
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#define ENABLE_IP_AUD0 0x0b00
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#define ENABLE_IP_AUD1 0x0b04
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static unsigned long aud_clk_regs[] __initdata = {
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MUX_SEL_AUD0,
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MUX_SEL_AUD1,
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MUX_ENABLE_AUD0,
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MUX_ENABLE_AUD1,
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MUX_STAT_AUD0,
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DIV_AUD0,
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DIV_AUD1,
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DIV_STAT_AUD0,
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DIV_STAT_AUD1,
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ENABLE_ACLK_AUD,
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ENABLE_PCLK_AUD,
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ENABLE_SCLK_AUD0,
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ENABLE_SCLK_AUD1,
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ENABLE_IP_AUD0,
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ENABLE_IP_AUD1,
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};
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/* list of all parent clock list */
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PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
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PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
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static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
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FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
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FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
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FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
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};
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static struct samsung_mux_clock aud_mux_clks[] __initdata = {
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/* MUX_SEL_AUD0 */
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MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
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mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
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/* MUX_SEL_AUD1 */
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MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
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MUX_SEL_AUD1, 8, 1),
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MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
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MUX_SEL_AUD1, 0, 1),
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};
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static struct samsung_div_clock aud_div_clks[] __initdata = {
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/* DIV_AUD0 */
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DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
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12, 4),
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DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
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8, 4),
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DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
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4, 4),
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DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
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0, 4),
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/* DIV_AUD1 */
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DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
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"mout_aud_pll_user", DIV_AUD1, 16, 5),
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DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
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DIV_AUD1, 12, 4),
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DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
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DIV_AUD1, 4, 8),
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DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
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DIV_AUD1, 0, 4),
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};
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static struct samsung_gate_clock aud_gate_clks[] __initdata = {
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/* ENABLE_ACLK_AUD */
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GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
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ENABLE_ACLK_AUD, 12, 0, 0),
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GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
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ENABLE_ACLK_AUD, 7, 0, 0),
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GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
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ENABLE_ACLK_AUD, 0, 4, 0),
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GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
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ENABLE_ACLK_AUD, 0, 3, 0),
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GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
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ENABLE_ACLK_AUD, 0, 2, 0),
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GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
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0, 1, 0),
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GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_AUD */
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GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
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13, 0, 0),
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GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
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12, 0, 0),
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GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
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11, 0, 0),
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GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
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ENABLE_PCLK_AUD, 10, 0, 0),
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GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
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ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
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ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
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ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
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ENABLE_PCLK_AUD, 6, 0, 0),
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GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
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ENABLE_PCLK_AUD, 5, 0, 0),
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GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
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ENABLE_PCLK_AUD, 4, 0, 0),
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GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
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ENABLE_PCLK_AUD, 3, 0, 0),
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GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
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2, 0, 0),
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GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
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ENABLE_PCLK_AUD, 0, 0, 0),
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/* ENABLE_SCLK_AUD0 */
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GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
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2, 0, 0),
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GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
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ENABLE_SCLK_AUD0, 1, 0, 0),
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GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
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0, 0, 0),
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/* ENABLE_SCLK_AUD1 */
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GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
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ENABLE_SCLK_AUD1, 6, 0, 0),
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GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
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ENABLE_SCLK_AUD1, 5, 0, 0),
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GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
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ENABLE_SCLK_AUD1, 4, 0, 0),
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GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
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ENABLE_SCLK_AUD1, 3, 0, 0),
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GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
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ENABLE_SCLK_AUD1, 2, 0, 0),
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GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
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ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
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ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
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};
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static struct samsung_cmu_info aud_cmu_info __initdata = {
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.mux_clks = aud_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
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.div_clks = aud_div_clks,
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.nr_div_clks = ARRAY_SIZE(aud_div_clks),
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.gate_clks = aud_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
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.fixed_clks = aud_fixed_clks,
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.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
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.nr_clk_ids = AUD_NR_CLK,
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.clk_regs = aud_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
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};
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static void __init exynos5433_cmu_aud_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &aud_cmu_info);
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}
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CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
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exynos5433_cmu_aud_init);
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@ -626,4 +626,57 @@
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#define DISP_NR_CLK 111
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/* CMU_AUD */
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#define CLK_MOUT_AUD_PLL_USER 1
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#define CLK_MOUT_SCLK_AUD_PCM 2
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#define CLK_MOUT_SCLK_AUD_I2S 3
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#define CLK_DIV_ATCLK_AUD 4
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#define CLK_DIV_PCLK_DBG_AUD 5
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#define CLK_DIV_ACLK_AUD 6
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#define CLK_DIV_AUD_CA5 7
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#define CLK_DIV_SCLK_AUD_SLIMBUS 8
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#define CLK_DIV_SCLK_AUD_UART 9
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#define CLK_DIV_SCLK_AUD_PCM 10
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#define CLK_DIV_SCLK_AUD_I2S 11
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#define CLK_ACLK_INTR_CTRL 12
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#define CLK_ACLK_AXIDS2_LPASSP 13
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#define CLK_ACLK_AXIDS1_LPASSP 14
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#define CLK_ACLK_AXI2APB1_LPASSP 15
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#define CLK_ACLK_AXI2APH_LPASSP 16
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#define CLK_ACLK_SMMU_LPASSX 17
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#define CLK_ACLK_AXIDS0_LPASSP 18
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#define CLK_ACLK_AXI2APB0_LPASSP 19
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#define CLK_ACLK_XIU_LPASSX 20
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#define CLK_ACLK_AUDNP_133 21
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#define CLK_ACLK_AUDND_133 22
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#define CLK_ACLK_SRAMC 23
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#define CLK_ACLK_DMAC 24
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#define CLK_PCLK_WDT1 25
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#define CLK_PCLK_WDT0 26
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#define CLK_PCLK_SFR1 27
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#define CLK_PCLK_SMMU_LPASSX 28
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#define CLK_PCLK_GPIO_AUD 29
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#define CLK_PCLK_PMU_AUD 30
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#define CLK_PCLK_SYSREG_AUD 31
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#define CLK_PCLK_AUD_SLIMBUS 32
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#define CLK_PCLK_AUD_UART 33
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#define CLK_PCLK_AUD_PCM 34
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#define CLK_PCLK_AUD_I2S 35
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#define CLK_PCLK_TIMER 36
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#define CLK_PCLK_SFR0_CTRL 37
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#define CLK_ATCLK_AUD 38
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#define CLK_PCLK_DBG_AUD 39
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#define CLK_SCLK_AUD_CA5 40
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#define CLK_SCLK_JTAG_TCK 41
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#define CLK_SCLK_SLIMBUS_CLKIN 42
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#define CLK_SCLK_AUD_SLIMBUS 43
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#define CLK_SCLK_AUD_UART 44
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#define CLK_SCLK_AUD_PCM 45
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#define CLK_SCLK_I2S_BCLK 46
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#define CLK_SCLK_AUD_I2S 47
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#define AUD_NR_CLK 48
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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