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iommu/arm-smmu: Clean up DMA API usage
With the correct DMA API calls now integrated into the io-pgtable code, let that handle the flushing of non-coherent page table updates. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -611,24 +611,13 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
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static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie)
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static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie)
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{
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{
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struct arm_smmu_domain *smmu_domain = cookie;
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struct arm_smmu_domain *smmu_domain = cookie;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
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/* Ensure new page tables are visible to the hardware walker */
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if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
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dsb(ishst);
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} else {
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/*
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/*
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* If the SMMU can't walk tables in the CPU caches, treat them
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* Ensure new page tables are visible to a coherent hardware walker.
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* like non-coherent DMA since we need to flush the new entries
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* The page table code deals with flushing for the non-coherent case.
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* all the way out to memory. There's no possibility of
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* recursion here as the SMMU table walker will not be wired
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* through another SMMU.
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*/
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*/
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dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
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if (smmu_domain->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
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DMA_TO_DEVICE);
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dsb(ishst);
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}
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}
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}
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static struct iommu_gather_ops arm_smmu_gather_ops = {
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static struct iommu_gather_ops arm_smmu_gather_ops = {
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@ -899,6 +888,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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.ias = ias,
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.ias = ias,
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.oas = oas,
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.oas = oas,
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.tlb = &arm_smmu_gather_ops,
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.tlb = &arm_smmu_gather_ops,
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.iommu_dev = smmu->dev,
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};
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};
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smmu_domain->smmu = smmu;
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smmu_domain->smmu = smmu;
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